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arm64: dts: meson: a1: add eMMC controller and its pins
The definition is inspired by a similar one for AXG SoC family.
'sdio_pins' and 'sdio_clk_gate_pins' pinctrls are supposed to be used as
"default" and "clk-gate" in board-specific device trees.
During initialization 'meson-gx' driver sets clock to safe low-frequency
value (400kHz). However, both source clocks ("clkin0" and "clkin1") are
high-frequency by default, and using of eMMC's internal divider is not
enough to achieve so low values. To provide low-frequency source,
reparent "sd_emmc_sel2" clock using 'assigned-clocks' property.
Signed-off-by: Jan Dakinevich <yvdakinevich@sberdevices.ru>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230823213630.12936-11-ddrokosov@sberdevices.ru
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
This commit is contained in:
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dba516fa19
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4d860a98bc
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@ -142,6 +142,32 @@ mux {
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bias-pull-down;
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};
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};
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sdio_pins: sdio {
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mux0 {
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groups = "sdcard_d0_x",
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"sdcard_d1_x",
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"sdcard_d2_x",
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"sdcard_d3_x",
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"sdcard_cmd_x";
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function = "sdcard";
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bias-pull-up;
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};
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mux1 {
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groups = "sdcard_clk_x";
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function = "sdcard";
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bias-disable;
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};
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};
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sdio_clk_gate_pins: sdio-clk-gate {
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mux {
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groups = "sdcard_clk_x";
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function = "sdcard";
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bias-pull-down;
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};
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};
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};
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gpio_intc: interrupt-controller@440 {
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@ -208,6 +234,23 @@ clkc_pll: pll-clock-controller@7c80 {
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<&clkc_periphs CLKID_HIFIPLL_IN>;
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clock-names = "fixpll_in", "hifipll_in";
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};
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sd_emmc: sd@10000 {
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compatible = "amlogic,meson-axg-mmc";
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reg = <0x0 0x10000 0x0 0x800>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc_periphs CLKID_SD_EMMC_A>,
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<&clkc_periphs CLKID_SD_EMMC>,
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<&clkc_pll CLKID_FCLK_DIV2>;
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clock-names = "core",
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"clkin0",
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"clkin1";
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assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_SEL2>;
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assigned-clock-parents = <&xtal>;
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resets = <&reset RESET_SD_EMMC_A>;
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power-domains = <&pwrc PWRC_SD_EMMC_ID>;
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status = "disabled";
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};
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};
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usb: usb@fe004400 {
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