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drm/amdgpu: cleanup idh event/req for NV headers

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1) drop the headers from AI in mxgpu_nv.c, should refer to mxgpu_nv.h

2) the IDH_EVENT_MAX is not used and not aligned with host side
   so drop it
3) the IDH_TEXT_MESSAG was provided in host but not defined in guest

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu 2020-03-03 16:40:00 +08:00 committed by Alex Deucher
parent ba56657d18
commit 4d130238a7
4 changed files with 26 additions and 3 deletions
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3
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h
View File

@ -46,7 +46,8 @@ enum idh_event {
IDH_SUCCESS,
IDH_FAIL,
IDH_QUERY_ALIVE,
IDH_EVENT_MAX
IDH_TEXT_MESSAGE = 255,
};
extern const struct amdgpu_virt_ops xgpu_ai_virt_ops;

1
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c
View File

@ -30,7 +30,6 @@
#include "navi10_ih.h"
#include "soc15_common.h"
#include "mxgpu_nv.h"
#include "mxgpu_ai.h"
static void xgpu_nv_mailbox_send_ack(struct amdgpu_device *adev)
{

22
drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h
View File

@ -28,6 +28,28 @@
#define NV_MAILBOX_POLL_MSG_TIMEDOUT 12000
#define NV_MAILBOX_POLL_FLR_TIMEDOUT 500
enum idh_request {
IDH_REQ_GPU_INIT_ACCESS = 1,
IDH_REL_GPU_INIT_ACCESS,
IDH_REQ_GPU_FINI_ACCESS,
IDH_REL_GPU_FINI_ACCESS,
IDH_REQ_GPU_RESET_ACCESS,
IDH_LOG_VF_ERROR = 200,
};
enum idh_event {
IDH_CLR_MSG_BUF = 0,
IDH_READY_TO_ACCESS_GPU,
IDH_FLR_NOTIFICATION,
IDH_FLR_NOTIFICATION_CMPL,
IDH_SUCCESS,
IDH_FAIL,
IDH_QUERY_ALIVE,
IDH_TEXT_MESSAGE = 255,
};
extern const struct amdgpu_virt_ops xgpu_nv_virt_ops;
void xgpu_nv_mailbox_set_irq_funcs(struct amdgpu_device *adev);

3
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.h
View File

@ -43,7 +43,8 @@ enum idh_event {
IDH_READY_TO_ACCESS_GPU,
IDH_FLR_NOTIFICATION,
IDH_FLR_NOTIFICATION_CMPL,
IDH_EVENT_MAX
IDH_TEXT_MESSAGE = 255
};
extern const struct amdgpu_virt_ops xgpu_vi_virt_ops;