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arm64: dts: add devicetree for TQMa91xx on MBa93xxCA
This allows using TQMa91xxCA / TQMa91xxLA SoM on MBa93xxCA starter kit. While not having display all other interfaces of this mainboard can be used. Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Markus Niebel
Frank Li
parent
174b7dfb7d
commit
4d0d3a3d19
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@ -586,6 +586,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb-can1.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin-peb-av-18.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba93xxca.dtb
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imx91-tqma9131-mba91xxca-lvds-tm070jvhg33-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-lvds-tm070jvhg33.dtbo
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imx91-tqma9131-mba91xxca-rgb-cdtech-dc44-dtbs := imx91-tqma9131-mba91xxca.dtb imx93-tqma9352-mba91xxca-rgb-cdtech-dc44.dtbo
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937
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts
Normal file
937
arch/arm64/boot/dts/freescale/imx91-tqma9131-mba93xxca.dts
Normal file
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@ -0,0 +1,937 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
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/*
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* Copyright (c) 2022-2026 TQ-Systems GmbH <linux@ew.tq-group.com>,
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* D-82229 Seefeld, Germany.
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* Author: Markus Niebel
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* Author: Alexander Stein
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*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx91-tqma9131.dtsi"
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/{
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model = "TQ-Systems i.MX91 TQMa91xxLA/TQMa91xxCA on MBa93xxCA starter kit";
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compatible = "tq,imx91-tqma9131-mba93xxca",
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"tq,imx91-tqma9131", "fsl,imx91";
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chassis-type = "embedded";
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chosen {
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stdout-path = &lpuart1;
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};
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aliases {
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eeprom0 = &eeprom0;
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ethernet0 = &eqos;
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ethernet1 = &fec;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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i2c0 = &lpi2c1;
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i2c1 = &lpi2c2;
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i2c2 = &lpi2c3;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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rtc0 = &pcf85063;
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rtc1 = &bbnsm_rtc;
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serial0 = &lpuart1;
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serial1 = &lpuart2;
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serial2 = &lpuart3;
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serial5 = &lpuart6;
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serial7 = &lpuart8;
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};
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clk_dp: clk-dp {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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status = "disabled";
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};
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fan0: pwm-fan {
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compatible = "pwm-fan";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwmfan>;
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fan-supply = <®_pwm_fan>;
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#cooling-cells = <2>;
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/* typical 25 kHz -> 40.000 nsec */
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pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>;
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cooling-levels = <0 32 64 128 196 240>;
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pulses-per-revolution = <2>;
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interrupt-parent = <&gpio2>;
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interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
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status = "disabled";
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};
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gpio-keys {
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compatible = "gpio-keys";
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autorepeat;
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switch-a {
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label = "switcha";
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linux,code = <BTN_0>;
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gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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switch-b {
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label = "switchb";
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linux,code = <BTN_1>;
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gpios = <&expander0 7 GPIO_ACTIVE_LOW>;
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wakeup-source;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led-1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&expander2 6 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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led-2 {
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color = <LED_COLOR_ID_AMBER>;
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function = LED_FUNCTION_HEARTBEAT;
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gpios = <&expander2 7 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>;
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};
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reg_3v3: regulator-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3_MB";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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reg_5v0: regulator-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_5V0_MB";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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reg_12v0: regulator-12v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_12V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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gpio = <&expander1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_mpcie_1v5: regulator-mpcie-1v5 {
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compatible = "regulator-fixed";
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regulator-name = "V_1V5_MPCIE";
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_mpcie_3v3: regulator-mpcie-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3_MPCIE";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_pwm_fan: regulator-pwm-fan {
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compatible = "regulator-fixed";
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regulator-name = "FAN_PWR";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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vin-supply = <®_12v0>;
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};
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thermal-zones {
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cpu-thermal {
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trips {
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cpu_active0: trip-active0 {
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temperature = <40000>;
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hysteresis = <5000>;
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type = "active";
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};
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cpu_active1: trip-active1 {
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temperature = <48000>;
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hysteresis = <3000>;
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type = "active";
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};
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cpu_active2: trip-active2 {
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temperature = <60000>;
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hysteresis = <10000>;
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type = "active";
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};
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};
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cooling-maps {
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map1 {
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trip = <&cpu_active0>;
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cooling-device = <&fan0 1 1>;
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};
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map2 {
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trip = <&cpu_active1>;
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cooling-device = <&fan0 2 2>;
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};
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map3 {
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trip = <&cpu_active2>;
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cooling-device = <&fan0 3 3>;
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};
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};
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};
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};
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};
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&adc1 {
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status = "okay";
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy_eqos>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy_eqos: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos_phy>;
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reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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interrupt-parent = <&gpio3>;
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interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
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enet-phy-lane-no-swap;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy_fec>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <5000000>;
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ethphy_fec: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec_phy>;
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reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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interrupt-parent = <&gpio3>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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enet-phy-lane-no-swap;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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};
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};
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_3v3>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_3v3>;
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status = "okay";
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};
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&gpio1 {
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gpio-line-names =
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/* 00 */ "", "", "USB_C_ALERT#", "PMIC_IRQ#",
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/* 04 */ "", "", "", "",
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/* 08 */ "", "", "", "BM2_TEMP_EVENT_MOD#",
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/* 12 */ "PEX_INT#", "", "RTC_EVENT#", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "", "",
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/* 28 */ "", "", "", "";
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};
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&gpio2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio2>;
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gpio-line-names =
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/* 00 */ "SPI6_PCS0#", "", "", "",
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/* 04 */ "", "", "", "SPI_CS#",
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/* 08 */ "", "FAN_RPM", "MIPI_CSI_TRIGGER", "MIPI_CSI_SYNC",
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/* 12 */ "", "", "", "",
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/* 16 */ "X1_11", "X1_21", "X1_17", "X1_13",
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/* 20 */ "X1_15", "X1_9", "", "",
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/* 24 */ "", "", "X1_7", "",
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/* 28 */ "", "", "", "";
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};
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&gpio3 {
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gpio-line-names =
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/* 00 */ "SD2_CD#", "", "", "",
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/* 04 */ "", "", "", "SD2_RST#",
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/* 08 */ "", "", "", "",
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/* 12 */ "", "", "", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "ENET1_INT#", "ENET2_INT#",
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/* 28 */ "", "", "", "";
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};
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&gpio4 {
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gpio-line-names =
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/* 00 */ "", "", "", "",
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/* 04 */ "", "", "", "",
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/* 08 */ "", "", "", "",
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/* 12 */ "", "", "", "",
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/* 16 */ "", "", "", "",
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/* 20 */ "", "", "", "",
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/* 24 */ "", "", "", "",
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/* 28 */ "", "DP_INT", "", "";
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};
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&lpi2c3 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3>;
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status = "okay";
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temperature-sensor@1c {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1c>;
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};
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ptn5110: usb-typec@50 {
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compatible = "nxp,ptn5110", "tcpci";
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reg = <0x50>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_typec>;
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interrupt-parent = <&gpio1>;
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interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
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connector {
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compatible = "usb-c-connector";
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label = "X17";
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power-role = "dual";
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data-role = "dual";
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try-power-role = "sink";
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typec-power-opmode = "default";
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pd-disable;
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self-powered;
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port {
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typec_con_hs: endpoint {
|
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remote-endpoint = <&typec_hs>;
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};
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};
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||||
};
|
||||
};
|
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|
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eeprom2: eeprom@54 {
|
||||
compatible = "nxp,se97b", "atmel,24c02";
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reg = <0x54>;
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pagesize = <16>;
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vcc-supply = <®_3v3>;
|
||||
};
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||||
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expander0: gpio@70 {
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compatible = "nxp,pca9538";
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reg = <0x70>;
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pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pexp_irq>;
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gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-parent = <&gpio1>;
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interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
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vcc-supply = <®_3v3>;
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gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#",
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"MPCIE_1V5_EN", "MPCIE_3V3_EN",
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"MPCIE_PERST#", "MPCIE_WDISABLE#",
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"BUTTON_A#", "BUTTON_B#";
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|
||||
mpcie-wake-hog {
|
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gpio-hog;
|
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gpios = <1 GPIO_ACTIVE_LOW>;
|
||||
input;
|
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line-name = "MPCIE_WAKE#";
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};
|
||||
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/*
|
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* Controls the mPCIE slot reset which is low active as
|
||||
* reset signal. The output-low states, the signal is
|
||||
* inactive, e.g. not in reset
|
||||
*/
|
||||
mpcie_rst_hog: mpcie-rst-hog {
|
||||
gpio-hog;
|
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gpios = <4 GPIO_ACTIVE_LOW>;
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output-low;
|
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line-name = "MPCIE_PERST#";
|
||||
};
|
||||
|
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/*
|
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* Controls the mPCIE slot WDISABLE pin which is low active
|
||||
* as disable signal. The output-low states, the signal is
|
||||
* inactive, e.g. not disabled
|
||||
*/
|
||||
mpcie_wdisable_hog: mpcie-wdisable-hog {
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "MPCIE_WDISABLE#";
|
||||
};
|
||||
};
|
||||
|
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expander1: gpio@71 {
|
||||
compatible = "nxp,pca9538";
|
||||
reg = <0x71>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <®_3v3>;
|
||||
gpio-line-names = "ENET1_RESET#", "ENET2_RESET#",
|
||||
"USB_RESET#", "",
|
||||
"WLAN_PD#", "WLAN_W_DISABLE#",
|
||||
"WLAN_PERST#", "12V_EN";
|
||||
|
||||
/*
|
||||
* Controls the WiFi card's low-active power down pin.
|
||||
* The output-low states, the signal is inactive,
|
||||
* resulting in high signal at power-down pin
|
||||
*/
|
||||
wlan-pd-hog {
|
||||
gpio-hog;
|
||||
gpios = <4 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "WLAN_PD#";
|
||||
};
|
||||
|
||||
/*
|
||||
* Controls the WiFi card's low-active disable pin.
|
||||
* The output-low states, the signal is inactive,
|
||||
* resulting in high signal at power-down pin
|
||||
*/
|
||||
wlan-wdisable-hog {
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "WLAN_W_DISABLE#";
|
||||
};
|
||||
|
||||
/*
|
||||
* Controls the WiFi card's reset pin.
|
||||
* The output-low states, the signal is inactive,
|
||||
* resulting in high signal at power-down pin
|
||||
*/
|
||||
wlan-perst-hog {
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "WLAN_PERST#";
|
||||
};
|
||||
};
|
||||
|
||||
expander2: gpio@72 {
|
||||
compatible = "nxp,pca9538";
|
||||
reg = <0x72>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <®_3v3>;
|
||||
gpio-line-names = "LCD_RESET#", "LCD_PWR_EN",
|
||||
"LCD_BLT_EN", "DP_EN",
|
||||
"MIPI_CSI_EN", "MIPI_CSI_RST#",
|
||||
"USER_LED1", "USER_LED2";
|
||||
};
|
||||
};
|
||||
|
||||
&lpi2c5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&pinctrl_lpi2c5>;
|
||||
pinctrl-1 = <&pinctrl_lpi2c5>;
|
||||
status = "okay";
|
||||
|
||||
dp_bridge: dp-bridge@f {
|
||||
compatible = "toshiba,tc9595", "toshiba,tc358767";
|
||||
reg = <0x0f>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tc9595>;
|
||||
clock-names = "ref";
|
||||
clocks = <&clk_dp>;
|
||||
reset-gpios = <&expander2 3 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-parent = <&gpio4>;
|
||||
interrupts = <29 IRQ_TYPE_EDGE_RISING>;
|
||||
toshiba,hpd-pin = <0>;
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
|
||||
dp_dsi_in: endpoint {
|
||||
data-lanes = <1 2 3 4>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lpspi6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_lpspi6_cs>;
|
||||
cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, <&gpio2 7 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&lpuart8 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcf85063 {
|
||||
/* RTC_EVENT# from SoM is connected on mainboard */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pcf85063>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
&se97_som {
|
||||
/* TEMP_EVENT# from SoM is connected on mainboard */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_temp_sensor_som>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
/* on LVDS connector, not usable */
|
||||
&tpm5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tpm5>;
|
||||
};
|
||||
|
||||
&tpm6 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tpm6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
dr_mode = "otg";
|
||||
hnp-disable;
|
||||
srp-disable;
|
||||
adp-disable;
|
||||
usb-role-switch;
|
||||
disable-over-current;
|
||||
samsung,picophy-pre-emp-curr-control = <3>;
|
||||
samsung,picophy-dc-vol-level-adjust = <7>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
typec_hs: endpoint {
|
||||
remote-endpoint = <&typec_con_hs>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
disable-over-current;
|
||||
samsung,picophy-pre-emp-curr-control = <3>;
|
||||
samsung,picophy-dc-vol-level-adjust = <7>;
|
||||
status = "okay";
|
||||
|
||||
hub_2_0: hub@1 {
|
||||
compatible = "usb424,2517";
|
||||
reg = <1>;
|
||||
reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>;
|
||||
vdd-supply = <®_3v3>;
|
||||
};
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
no-mmc;
|
||||
disable-wp;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl_eqos: eqosgrp {
|
||||
fsl,pins = <
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_ENET1_MDC__ENET1_MDC 0x51e
|
||||
/* SION | HYS | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e
|
||||
/* HYS | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000
|
||||
MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000
|
||||
MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000
|
||||
MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000
|
||||
MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000
|
||||
/* HYS | PD | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x1400
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e
|
||||
MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x51e
|
||||
MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e
|
||||
MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e
|
||||
MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e
|
||||
/* PD | FSEL_3 | DSE X3 */
|
||||
MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_eqos_phy: eqosphygrp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec: fecgrp {
|
||||
fsl,pins = <
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_ENET2_MDC__ENET2_MDC 0x51e
|
||||
/* SION | HYS | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x4000111e
|
||||
/* HYS | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x1000
|
||||
MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x1000
|
||||
MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x1000
|
||||
MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x1000
|
||||
MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x1000
|
||||
/* HYS | PD | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x1400
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x51e
|
||||
MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x51e
|
||||
MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x51e
|
||||
MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x51e
|
||||
MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x51e
|
||||
/* PD | FSEL_3 | DSE X3 */
|
||||
MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x58e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_fec_phy: fecphygrp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp {
|
||||
fsl,pins = <
|
||||
/* HYS | PU | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200
|
||||
/* PU | FSEL_3 | DSE X4 */
|
||||
MX91_PAD_PDM_CLK__CAN1_TX 0x039e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp {
|
||||
fsl,pins = <
|
||||
/* HYS | PU | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_GPIO_IO27__CAN2_RX 0x1200
|
||||
/* PU | FSEL_3 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO25__CAN2_TX 0x039e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio2: gpio2grp {
|
||||
fsl,pins = <
|
||||
/* HYS | PD | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO16__GPIO2_IO16 0x151e
|
||||
MX91_PAD_GPIO_IO17__GPIO2_IO17 0x151e
|
||||
MX91_PAD_GPIO_IO18__GPIO2_IO18 0x151e
|
||||
MX91_PAD_GPIO_IO19__GPIO2_IO19 0x151e
|
||||
MX91_PAD_GPIO_IO20__GPIO2_IO20 0x151e
|
||||
MX91_PAD_GPIO_IO21__GPIO2_IO21 0x151e
|
||||
MX91_PAD_GPIO_IO26__GPIO2_IO26 0x151e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_jtag: jtaggrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e
|
||||
MX91_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200
|
||||
MX91_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e
|
||||
MX91_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpi2c3: lpi2c3grp {
|
||||
fsl,pins = <
|
||||
/* SION | HYS | OD | FSEL_3 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e
|
||||
MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpi2c5: lpi2c5grp {
|
||||
fsl,pins = <
|
||||
/* SION | HYS | OD | FSEL_3 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO22__LPI2C5_SDA 0x4000199e
|
||||
MX91_PAD_GPIO_IO23__LPI2C5_SCL 0x4000199e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpspi6: lpspi6grp {
|
||||
fsl,pins = <
|
||||
/* HYS | PD | FSEL_0 | DSE no drive */
|
||||
MX91_PAD_GPIO_IO01__LPSPI6_SIN 0x1400
|
||||
/* PD | FSEL_2 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO02__LPSPI6_SOUT 0x051e
|
||||
MX91_PAD_GPIO_IO03__LPSPI6_SCK 0x051e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lpspi6_cs: lpspi6csgrp {
|
||||
fsl,pins = <
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO00__GPIO2_IO0 0x011e
|
||||
MX91_PAD_GPIO_IO07__GPIO2_IO7 0x011e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mipi_csi: mipicsigrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x051e /* MCLK */
|
||||
MX91_PAD_GPIO_IO10__GPIO2_IO10 0x051e /* TRIGGER */
|
||||
MX91_PAD_GPIO_IO11__GPIO2_IO11 0x1400 /* SYNC */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pcf85063: pcf85063grp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pexp_irq: pexpirqgrp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_SAI1_TXC__GPIO1_IO12 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwmfan: pwmfangrp {
|
||||
fsl,pins = <
|
||||
/* HYS | PU | FSEL_0 | no DSE */
|
||||
MX91_PAD_GPIO_IO09__GPIO2_IO9 0x1200
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tc9595: tc9595-grp {
|
||||
fsl,pins = <
|
||||
/* HYS | PD | FSEL_0 | no DSE */
|
||||
MX91_PAD_CCM_CLKO4__GPIO4_IO29 0x1400
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_temp_sensor_som: tempsensorsomgrp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | no DSE */
|
||||
MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tpm5: tpm5grp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_GPIO_IO06__TPM5_CH0 0x57e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tpm6: tpm6grp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_GPIO_IO08__TPM6_CH0 0x57e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_typec: typecgrp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_I2C2_SCL__GPIO1_IO2 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_UART1_RXD__LPUART1_RX 0x1000
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_UART1_TXD__LPUART1_TX 0x011e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_UART2_RXD__LPUART2_RX 0x1000
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_UART2_TXD__LPUART2_TX 0x011e
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_GPIO_IO15__LPUART3_RX 0x1000
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO14__LPUART3_TX 0x011e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart6: uart6grp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_GPIO_IO05__LPUART6_RX 0x1000
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO04__LPUART6_TX 0x011e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart8: uart8grp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_GPIO_IO13__LPUART8_RX 0x1000
|
||||
/* FSEL_2 | DSE X4 */
|
||||
MX91_PAD_GPIO_IO12__LPUART8_TX 0x011e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
||||
fsl,pins = <
|
||||
/* HYS | FSEL_0 | No DSE */
|
||||
MX91_PAD_SD2_CD_B__GPIO3_IO0 0x1000
|
||||
>;
|
||||
};
|
||||
|
||||
/* enable SION for data and cmd pad due to ERR052021 */
|
||||
pinctrl_usdhc2_hs: usdhc2hsgrp {
|
||||
fsl,pins = <
|
||||
/* PD | FSEL_3 | DSE X5 */
|
||||
MX91_PAD_SD2_CLK__USDHC2_CLK 0x05be
|
||||
/* HYS | PU | FSEL_3 | DSE X4 */
|
||||
MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
|
||||
/* HYS | PU | FSEL_3 | DSE X3 */
|
||||
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
|
||||
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
|
||||
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
|
||||
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
|
||||
/* FSEL_2 | DSE X3 */
|
||||
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
|
||||
>;
|
||||
};
|
||||
|
||||
/* enable SION for data and cmd pad due to ERR052021 */
|
||||
pinctrl_usdhc2_uhs: usdhc2uhsgrp {
|
||||
fsl,pins = <
|
||||
/* PD | FSEL_3 | DSE X6 */
|
||||
MX91_PAD_SD2_CLK__USDHC2_CLK 0x05fe
|
||||
/* HYS | PU | FSEL_3 | DSE X4 */
|
||||
MX91_PAD_SD2_CMD__USDHC2_CMD 0x4000139e
|
||||
MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e
|
||||
MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e
|
||||
MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e
|
||||
MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e
|
||||
/* FSEL_2 | DSE X3 */
|
||||
MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user