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drm/xe: Cleanup SPACING style issues

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Remove almost all existing style issues of type SPACING reported
by checkpatch.

Signed-off-by: Francois Dugast <francois.dugast@intel.com>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Francois Dugast 2023-07-11 16:24:30 +02:00 committed by Rodrigo Vivi
parent 04194a4f78
commit 4cd6d49259
10 changed files with 24 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/gpu/drm/xe/xe_device.h
View File

@ -122,7 +122,7 @@ static inline void xe_device_guc_submission_disable(struct xe_device *xe)
#define for_each_tile(tile__, xe__, id__) \
for ((id__) = 0; (id__) < (xe__)->info.tile_count; (id__)++) \
for_each_if ((tile__) = &(xe__)->tiles[(id__)])
for_each_if((tile__) = &(xe__)->tiles[(id__)])
/*
* FIXME: This only works for now since multi-tile and standalone media
@ -130,7 +130,7 @@ static inline void xe_device_guc_submission_disable(struct xe_device *xe)
*/
#define for_each_gt(gt__, xe__, id__) \
for ((id__) = 0; (id__) < (xe__)->info.gt_count; (id__)++) \
for_each_if ((gt__) = xe_device_get_gt((xe__), (id__)))
for_each_if((gt__) = xe_device_get_gt((xe__), (id__)))
static inline struct xe_force_wake * gt_to_fw(struct xe_gt *gt)
{

4
drivers/gpu/drm/xe/xe_device_types.h
View File

@ -47,8 +47,8 @@ struct xe_ggtt;
#define tile_to_xe(tile__) \
_Generic(tile__, \
const struct xe_tile *: (const struct xe_device *)((tile__)->xe), \
struct xe_tile *: (tile__)->xe)
const struct xe_tile * : (const struct xe_device *)((tile__)->xe), \
struct xe_tile * : (tile__)->xe)
/**
* struct xe_tile - hardware tile structure

2
drivers/gpu/drm/xe/xe_force_wake.c
View File

@ -87,7 +87,7 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw)
BIT(0), BIT(16));
}
for (i = XE_HW_ENGINE_VECS0, j =0; i <= XE_HW_ENGINE_VECS3; ++i, ++j) {
for (i = XE_HW_ENGINE_VECS0, j = 0; i <= XE_HW_ENGINE_VECS3; ++i, ++j) {
if (!(gt->info.engine_mask & BIT(i)))
continue;

2
drivers/gpu/drm/xe/xe_gt.h
View File

@ -13,7 +13,7 @@
#define for_each_hw_engine(hwe__, gt__, id__) \
for ((id__) = 0; (id__) < ARRAY_SIZE((gt__)->hw_engines); (id__)++) \
for_each_if (((hwe__) = (gt__)->hw_engines + (id__)) && \
for_each_if(((hwe__) = (gt__)->hw_engines + (id__)) && \
xe_hw_engine_is_valid((hwe__)))
struct xe_gt *xe_gt_alloc(struct xe_tile *tile);

8
drivers/gpu/drm/xe/xe_gt_clock.c
View File

@ -38,13 +38,13 @@ static u32 get_crystal_clock_freq(u32 rpm_config_reg)
rpm_config_reg);
switch (crystal_clock) {
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ :
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
return f24_mhz;
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ :
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
return f19_2_mhz;
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ :
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
return f38_4_mhz;
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ :
case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
return f25_mhz;
default:
XE_BUG_ON("NOT_POSSIBLE");

8
drivers/gpu/drm/xe/xe_gt_types.h
View File

@ -75,13 +75,13 @@ enum xe_steering_type {
#define gt_to_tile(gt__) \
_Generic(gt__, \
const struct xe_gt *: (const struct xe_tile *)((gt__)->tile), \
struct xe_gt *: (gt__)->tile)
const struct xe_gt * : (const struct xe_tile *)((gt__)->tile), \
struct xe_gt * : (gt__)->tile)
#define gt_to_xe(gt__) \
_Generic(gt__, \
const struct xe_gt *: (const struct xe_device *)(gt_to_tile(gt__)->xe), \
struct xe_gt *: gt_to_tile(gt__)->xe)
const struct xe_gt * : (const struct xe_device *)(gt_to_tile(gt__)->xe), \
struct xe_gt * : gt_to_tile(gt__)->xe)
/**
* struct xe_gt - A "Graphics Technology" unit of the GPU

4
drivers/gpu/drm/xe/xe_rtp.h
View File

@ -373,8 +373,8 @@ struct xe_reg_sr;
}
#define XE_RTP_PROCESS_CTX_INITIALIZER(arg__) _Generic((arg__), \
struct xe_hw_engine *: (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE }, \
struct xe_gt *: (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT })
struct xe_hw_engine * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_ENGINE }, \
struct xe_gt * : (struct xe_rtp_process_ctx){ { (void *)(arg__) }, XE_RTP_PROCESS_TYPE_GT })
void xe_rtp_process_ctx_enable_active_tracking(struct xe_rtp_process_ctx *ctx,
unsigned long *active_entries,

10
drivers/gpu/drm/xe/xe_rtp_helpers.h
View File

@ -14,13 +14,13 @@
* Helper macros - not to be used outside this header.
*/
#define _XE_ESC(...) __VA_ARGS__
#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__,5,4,3,2,1,))
#define __XE_COUNT_ARGS(_,_5,_4,_3,_2,X_,...) X_
#define _XE_COUNT_ARGS(...) _XE_ESC(__XE_COUNT_ARGS(__VA_ARGS__, 5, 4, 3, 2, 1,))
#define __XE_COUNT_ARGS(_, _5, _4, _3, _2, X_, ...) X_
#define _XE_FIRST(...) _XE_ESC(__XE_FIRST(__VA_ARGS__,))
#define __XE_FIRST(x_,...) x_
#define __XE_FIRST(x_, ...) x_
#define _XE_TUPLE_TAIL(...) _XE_ESC(__XE_TUPLE_TAIL(__VA_ARGS__))
#define __XE_TUPLE_TAIL(x_,...) (__VA_ARGS__)
#define __XE_TUPLE_TAIL(x_, ...) (__VA_ARGS__)
#define _XE_DROP_FIRST(x_, ...) __VA_ARGS__
@ -59,7 +59,7 @@
*
* XE_RTP_TEST_FOO BANANA XE_RTP_TEST_BAR
*/
#define XE_RTP_PASTE_FOREACH(prefix_, sep_, args_) _XE_ESC(_XE_RTP_CONCAT(PASTE_,_XE_COUNT_ARGS args_)(prefix_, sep_, args_))
#define XE_RTP_PASTE_FOREACH(prefix_, sep_, args_) _XE_ESC(_XE_RTP_CONCAT(PASTE_, _XE_COUNT_ARGS args_)(prefix_, sep_, args_))
#define XE_RTP_PASTE_1(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_)
#define XE_RTP_PASTE_2(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_1(prefix_, sep_, _XE_TUPLE_TAIL args_)
#define XE_RTP_PASTE_3(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, _XE_FIRST args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_2(prefix_, sep_, _XE_TUPLE_TAIL args_)

2
drivers/gpu/drm/xe/xe_sched_job.c
View File

@ -35,7 +35,7 @@ int __init xe_sched_job_module_init(void)
kmem_cache_create("xe_sched_job_parallel",
sizeof(struct xe_sched_job) +
sizeof(u64) *
XE_HW_ENGINE_MAX_INSTANCE , 0,
XE_HW_ENGINE_MAX_INSTANCE, 0,
SLAB_HWCACHE_ALIGN, NULL);
if (!xe_sched_job_parallel_slab) {
kmem_cache_destroy(xe_sched_job_slab);

4
drivers/gpu/drm/xe/xe_uc_fw.c
View File

@ -100,8 +100,8 @@ struct fw_blobs_by_type {
};
#define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
fw_def(METEORLAKE, mmp_ver( i915, guc, mtl, 70, 6, 4)) \
fw_def(PVC, mmp_ver( xe, guc, pvc, 70, 6, 4)) \
fw_def(METEORLAKE, mmp_ver(i915, guc, mtl, 70, 6, 4)) \
fw_def(PVC, mmp_ver(xe, guc, pvc, 70, 6, 4)) \
fw_def(DG2, major_ver(i915, guc, dg2, 70, 5)) \
fw_def(DG1, major_ver(i915, guc, dg1, 70, 5)) \
fw_def(ALDERLAKE_N, major_ver(i915, guc, tgl, 70, 5)) \