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drm/amd/pm: Fetch partition metrics on SMUv13.0.6
Add support to fetch compute partition related metrics in SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Asad Kamal <asad.kamal@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2536,6 +2536,117 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
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return pcie_gen_to_speed(speed_level + 1);
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}
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static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
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void *table)
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{
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const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
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int version = smu_v13_0_6_get_metrics_version(smu);
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struct amdgpu_partition_metrics_v1_0 *xcp_metrics;
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struct amdgpu_device *adev = smu->adev;
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int ret, inst, i, j, k, idx;
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MetricsTableV0_t *metrics_v0;
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MetricsTableV1_t *metrics_v1;
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MetricsTableV2_t *metrics_v2;
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struct amdgpu_xcp *xcp;
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u32 inst_mask;
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bool per_inst;
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if (!table)
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return sizeof(*xcp_metrics);
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for_each_xcp(adev->xcp_mgr, xcp, i) {
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if (xcp->id == xcp_id)
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break;
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}
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if (i == adev->xcp_mgr->num_xcps)
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return -EINVAL;
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xcp_metrics = (struct amdgpu_partition_metrics_v1_0 *)table;
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smu_cmn_init_partition_metrics(xcp_metrics, 1, 0);
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metrics_v0 = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
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if (!metrics_v0)
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return -ENOMEM;
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ret = smu_v13_0_6_get_metrics_table(smu, metrics_v0, false);
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if (ret) {
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kfree(metrics_v0);
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return ret;
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}
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metrics_v1 = (MetricsTableV1_t *)metrics_v0;
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metrics_v2 = (MetricsTableV2_t *)metrics_v0;
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per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
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amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
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idx = 0;
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for_each_inst(k, inst_mask) {
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/* Both JPEG and VCN has same instances */
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inst = GET_INST(VCN, k);
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for (j = 0; j < num_jpeg_rings; ++j) {
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xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] =
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SMUQ10_ROUND(GET_METRIC_FIELD(
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JpegBusy,
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version)[(inst * num_jpeg_rings) + j]);
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}
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xcp_metrics->vcn_busy[idx] =
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SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
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xcp_metrics->current_vclk0[idx] = SMUQ10_ROUND(
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GET_METRIC_FIELD(VclkFrequency, version)[inst]);
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xcp_metrics->current_dclk0[idx] = SMUQ10_ROUND(
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GET_METRIC_FIELD(DclkFrequency, version)[inst]);
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xcp_metrics->current_socclk[idx] = SMUQ10_ROUND(
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GET_METRIC_FIELD(SocclkFrequency, version)[inst]);
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idx++;
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}
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xcp_metrics->current_uclk =
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SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
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if (per_inst) {
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amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
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idx = 0;
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for_each_inst(k, inst_mask) {
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inst = GET_INST(GC, k);
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xcp_metrics->current_gfxclk[idx] =
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SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency,
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version)[inst]);
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xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(
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GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
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xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(
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GET_GPU_METRIC_FIELD(GfxBusyAcc,
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version)[inst]);
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if (smu_v13_0_6_cap_supported(
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smu, SMU_CAP(HST_LIMIT_METRICS))) {
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xcp_metrics->gfx_below_host_limit_ppt_acc
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[idx] = SMUQ10_ROUND(
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metrics_v0->GfxclkBelowHostLimitPptAcc
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[inst]);
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xcp_metrics->gfx_below_host_limit_thm_acc
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[idx] = SMUQ10_ROUND(
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metrics_v0->GfxclkBelowHostLimitThmAcc
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[inst]);
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xcp_metrics->gfx_low_utilization_acc
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[idx] = SMUQ10_ROUND(
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metrics_v0
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->GfxclkLowUtilizationAcc[inst]);
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xcp_metrics->gfx_below_host_limit_total_acc
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[idx] = SMUQ10_ROUND(
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metrics_v0->GfxclkBelowHostLimitTotalAcc
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[inst]);
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}
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idx++;
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}
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}
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kfree(metrics_v0);
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return sizeof(*xcp_metrics);
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}
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static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
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{
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struct smu_table_context *smu_table = &smu->smu_table;
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@ -3680,6 +3791,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
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.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
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.get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
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.get_pm_metrics = smu_v13_0_6_get_pm_metrics,
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.get_xcp_metrics = smu_v13_0_6_get_xcp_metrics,
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.get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
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.mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
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.link_reset_is_support = smu_v13_0_6_is_link_reset_supported,
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