Add support for GPIO based CS

Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>:

The Microchip PolarFire SoC SPI "hard" controller supports eight
chip selects. However, only one chip select is physically wired.
Therefore, use GPIO descriptors to configure additional chip select
lines.
This commit is contained in:
Mark Brown 2024-05-29 11:24:37 +01:00
commit 4ccaf60062
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2 changed files with 31 additions and 4 deletions

View File

@ -13,9 +13,6 @@ description:
maintainers:
- Conor Dooley <conor.dooley@microchip.com>
allOf:
- $ref: spi-controller.yaml#
properties:
compatible:
oneOf:
@ -43,6 +40,32 @@ required:
- interrupts
- clocks
allOf:
- $ref: spi-controller.yaml#
- if:
properties:
compatible:
contains:
const: microchip,mpfs-spi
then:
properties:
num-cs:
default: 1
- if:
properties:
compatible:
contains:
const: microchip,mpfs-spi
not:
required:
- cs-gpios
then:
properties:
num-cs:
maximum: 1
unevaluatedProperties: false
examples:

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@ -21,7 +21,7 @@
#include <linux/spi/spi.h>
#define MAX_LEN (0xffff)
#define MAX_CS (8)
#define MAX_CS (1)
#define DEFAULT_FRAMESIZE (8)
#define FIFO_DEPTH (32)
#define CLK_GEN_MODE1_MAX (255)
@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi)
struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
u32 reg;
if (spi_is_csgpiod(spi))
return 0;
/*
* Active high targets need to be specifically set to their inactive
* states during probe by adding them to the "control group" & thus
@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
host->num_chipselect = num_cs;
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
host->use_gpio_descriptors = true;
host->setup = mchp_corespi_setup;
host->bits_per_word_mask = SPI_BPW_MASK(8);
host->transfer_one = mchp_corespi_transfer_one;