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Add support for GPIO based CS
Merge series from Prajna Rajendra Kumar <prajna.rajendrakumar@microchip.com>: The Microchip PolarFire SoC SPI "hard" controller supports eight chip selects. However, only one chip select is physically wired. Therefore, use GPIO descriptors to configure additional chip select lines.
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commit
4ccaf60062
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@ -13,9 +13,6 @@ description:
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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allOf:
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- $ref: spi-controller.yaml#
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properties:
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compatible:
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oneOf:
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@ -43,6 +40,32 @@ required:
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- interrupts
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- clocks
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: microchip,mpfs-spi
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then:
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properties:
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num-cs:
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default: 1
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- if:
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properties:
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compatible:
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contains:
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const: microchip,mpfs-spi
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not:
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required:
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- cs-gpios
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then:
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properties:
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num-cs:
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maximum: 1
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unevaluatedProperties: false
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examples:
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@ -21,7 +21,7 @@
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#include <linux/spi/spi.h>
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#define MAX_LEN (0xffff)
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#define MAX_CS (8)
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#define MAX_CS (1)
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#define DEFAULT_FRAMESIZE (8)
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#define FIFO_DEPTH (32)
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#define CLK_GEN_MODE1_MAX (255)
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@ -258,6 +258,9 @@ static int mchp_corespi_setup(struct spi_device *spi)
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struct mchp_corespi *corespi = spi_controller_get_devdata(spi->controller);
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u32 reg;
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if (spi_is_csgpiod(spi))
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return 0;
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/*
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* Active high targets need to be specifically set to their inactive
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* states during probe by adding them to the "control group" & thus
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@ -516,6 +519,7 @@ static int mchp_corespi_probe(struct platform_device *pdev)
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host->num_chipselect = num_cs;
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host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
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host->use_gpio_descriptors = true;
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host->setup = mchp_corespi_setup;
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host->bits_per_word_mask = SPI_BPW_MASK(8);
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host->transfer_one = mchp_corespi_transfer_one;
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