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drm/i915/display: move watermark funcs under wm sub-struct

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Move watermark related functions under wm sub-struct of struct
intel_display.

The funcs sub-struct of struct intel_display seems unnecessary. Instead
of display->funcs.FEATURE, prefer display->FEATURE.funcs.

Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
Link: https://patch.msgid.link/6b74ab66692dce20b2a6a8cb8cfdef222b2983ca.1777537663.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2026-04-30 11:28:48 +03:00
parent 5a6447dd10
commit 4c5e172872
5 changed files with 32 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/i915/display/i9xx_wm.c
View File

@ -3584,7 +3584,7 @@ void ilk_wm_sanitize(struct intel_display *display)
int i;
/* Only supported on platforms that use atomic watermark design */
if (!display->funcs.wm->optimize_watermarks)
if (!display->wm.funcs->optimize_watermarks)
return;
if (drm_WARN_ON(display->drm, DISPLAY_VER(display) >= 9))
@ -4152,34 +4152,34 @@ void i9xx_wm_init(struct intel_display *display)
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(display)) {
ilk_setup_wm_latency(display);
display->funcs.wm = &ilk_wm_funcs;
display->wm.funcs = &ilk_wm_funcs;
} else if (display->platform.valleyview || display->platform.cherryview) {
vlv_setup_wm_latency(display);
display->funcs.wm = &vlv_wm_funcs;
display->wm.funcs = &vlv_wm_funcs;
} else if (display->platform.g4x) {
g4x_setup_wm_latency(display);
display->funcs.wm = &g4x_wm_funcs;
display->wm.funcs = &g4x_wm_funcs;
} else if (display->platform.pineview) {
if (!pnv_get_cxsr_latency(display)) {
drm_info(display->drm, "Unknown FSB/MEM, disabling CxSR\n");
/* Disable CxSR and never update its watermark again */
intel_set_memory_cxsr(display, false);
display->funcs.wm = &nop_funcs;
display->wm.funcs = &nop_funcs;
} else {
display->funcs.wm = &pnv_wm_funcs;
display->wm.funcs = &pnv_wm_funcs;
}
} else if (DISPLAY_VER(display) == 4) {
display->funcs.wm = &i965_wm_funcs;
display->wm.funcs = &i965_wm_funcs;
} else if (DISPLAY_VER(display) == 3) {
display->funcs.wm = &i9xx_wm_funcs;
display->wm.funcs = &i9xx_wm_funcs;
} else if (DISPLAY_VER(display) == 2) {
if (INTEL_NUM_PIPES(display) == 1)
display->funcs.wm = &i845_wm_funcs;
display->wm.funcs = &i845_wm_funcs;
else
display->funcs.wm = &i9xx_wm_funcs;
display->wm.funcs = &i9xx_wm_funcs;
} else {
drm_err(display->drm,
"unexpected fall-through in %s\n", __func__);
display->funcs.wm = &nop_funcs;
display->wm.funcs = &nop_funcs;
}
}

2
drivers/gpu/drm/i915/display/intel_display.c
View File

@ -2162,7 +2162,7 @@ static void i9xx_crtc_disable(struct intel_atomic_state *state,
if (DISPLAY_VER(display) != 2)
intel_set_cpu_fifo_underrun_reporting(display, pipe, false);
if (!display->funcs.wm->initial_watermarks)
if (!display->wm.funcs->initial_watermarks)
intel_update_watermarks(display);
/* clock the pipe down to 640x480@60 to potentially save power */

6
drivers/gpu/drm/i915/display/intel_display_core.h
View File

@ -247,6 +247,9 @@ struct intel_vbt_data {
};
struct intel_wm {
/* internal watermark functions */
const struct intel_wm_funcs *funcs;
/*
* Raw watermark latency values:
* in 0.1us units for WM0,
@ -313,9 +316,6 @@ struct intel_display {
/* irq display functions */
const struct intel_hotplug_funcs *hotplug;
/* pm display functions */
const struct intel_wm_funcs *wm;
} funcs;
struct {

32
drivers/gpu/drm/i915/display/intel_wm.c
View File

@ -48,8 +48,8 @@
*/
void intel_update_watermarks(struct intel_display *display)
{
if (display->funcs.wm->update_wm)
display->funcs.wm->update_wm(display);
if (display->wm.funcs->update_wm)
display->wm.funcs->update_wm(display);
}
int intel_wm_compute(struct intel_atomic_state *state,
@ -57,10 +57,10 @@ int intel_wm_compute(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
if (!display->funcs.wm->compute_watermarks)
if (!display->wm.funcs->compute_watermarks)
return 0;
return display->funcs.wm->compute_watermarks(state, crtc);
return display->wm.funcs->compute_watermarks(state, crtc);
}
bool intel_initial_watermarks(struct intel_atomic_state *state,
@ -68,8 +68,8 @@ bool intel_initial_watermarks(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
if (display->funcs.wm->initial_watermarks) {
display->funcs.wm->initial_watermarks(state, crtc);
if (display->wm.funcs->initial_watermarks) {
display->wm.funcs->initial_watermarks(state, crtc);
return true;
}
@ -81,8 +81,8 @@ void intel_atomic_update_watermarks(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
if (display->funcs.wm->atomic_update_watermarks)
display->funcs.wm->atomic_update_watermarks(state, crtc);
if (display->wm.funcs->atomic_update_watermarks)
display->wm.funcs->atomic_update_watermarks(state, crtc);
}
void intel_optimize_watermarks(struct intel_atomic_state *state,
@ -90,30 +90,30 @@ void intel_optimize_watermarks(struct intel_atomic_state *state,
{
struct intel_display *display = to_intel_display(state);
if (display->funcs.wm->optimize_watermarks)
display->funcs.wm->optimize_watermarks(state, crtc);
if (display->wm.funcs->optimize_watermarks)
display->wm.funcs->optimize_watermarks(state, crtc);
}
int intel_compute_global_watermarks(struct intel_atomic_state *state)
{
struct intel_display *display = to_intel_display(state);
if (display->funcs.wm->compute_global_watermarks)
return display->funcs.wm->compute_global_watermarks(state);
if (display->wm.funcs->compute_global_watermarks)
return display->wm.funcs->compute_global_watermarks(state);
return 0;
}
void intel_wm_get_hw_state(struct intel_display *display)
{
if (display->funcs.wm->get_hw_state)
return display->funcs.wm->get_hw_state(display);
if (display->wm.funcs->get_hw_state)
return display->wm.funcs->get_hw_state(display);
}
void intel_wm_sanitize(struct intel_display *display)
{
if (display->funcs.wm->sanitize)
return display->funcs.wm->sanitize(display);
if (display->wm.funcs->sanitize)
return display->wm.funcs->sanitize(display);
}
bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state,

2
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -3995,7 +3995,7 @@ void skl_wm_init(struct intel_display *display)
skl_setup_wm_latency(display);
display->funcs.wm = &skl_wm_funcs;
display->wm.funcs = &skl_wm_funcs;
}
static int skl_watermark_ipc_status_show(struct seq_file *m, void *data)