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arm64: dts: mediatek: mt8195-cherry-dojo: Describe M.2 M-key NVMe slot

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The Dojo device has a M.2 M-key slot for an included NVMe on some
models.

Add a proper device tree description based on the new M.2 M-key binding.
Power for the slot is controlled by the embedded controller. As far as
the main SoC is concerned, it is always on.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
Chen-Yu Tsai 2026-03-02 13:31:07 +08:00 committed by AngeloGioacchino Del Regno
parent 0c5d91b3d0
commit 4c434585ce
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GPG Key ID: 9A3604CFAD978478
1 changed files with 38 additions and 0 deletions
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38
arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts
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@ -11,6 +11,28 @@ / {
compatible = "google,dojo-sku7", "google,dojo-sku5",
"google,dojo-sku3", "google,dojo-sku1",
"google,dojo", "mediatek,mt8195";
nvme-connector {
compatible = "pcie-m2-m-connector";
/* power is controlled by EC */
vpcie3v3-supply = <&pp3300_z2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
nvme_ep: endpoint@0 {
reg = <0>;
remote-endpoint = <&pcie0_ep>;
};
};
};
};
};
&audio_codec {
@ -72,6 +94,22 @@ &pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie0_pins_default>;
status = "okay";
pcie@0 {
compatible = "pciclass,0604";
reg = <0 0 0 0 0>;
device_type = "pci";
num-lanes = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
port {
pcie0_ep: endpoint {
remote-endpoint = <&nvme_ep>;
};
};
};
};
&pciephy {