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regulator: Add regulator driver for Unisoc SC2730 PMIC
Add a regulator driver for the Spreadtrum/Unisoc SC2730 PMIC, used
e.g. with the UMS512 and UMS9230 SoCs. This version of the driver is
based on a downstream driver provided by Unisoc [1][2] and the existing
SC2731 driver.
[1]: 30be0ddfe6
[2]: https://github.com/MotorolaMobilityLLC/kernel-sprd/blob/android-13-release-tla33/drivers/regulator/sc2730-regulator.c
Signed-off-by: Zhongfa Wang <zhongfa.wang@unisoc.com>
[cleanup, adapt to new device tree requirements]
Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Link: https://patch.msgid.link/20260701-sc2730-regulators-v7-2-6e145ce83657@abscue.de
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Otto Pflüger
Mark Brown
parent
7c8cc25d8d
commit
4c40e28e83
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@ -1477,6 +1477,13 @@ config REGULATOR_S5M8767
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via I2C bus. S5M8767A have 9 Bucks and 28 LDOs output and
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supports DVS mode with 8bits of output voltage control.
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config REGULATOR_SC2730
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tristate "Spreadtrum SC2730 power regulator driver"
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depends on MFD_SC27XX_PMIC || COMPILE_TEST
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help
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This driver provides support for the voltage regulators on the
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SC2730 PMIC.
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config REGULATOR_SC2731
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tristate "Spreadtrum SC2731 power regulator driver"
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depends on MFD_SC27XX_PMIC || COMPILE_TEST
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@ -170,6 +170,7 @@ obj-$(CONFIG_REGULATOR_S2DOS05) += s2dos05-regulator.o
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obj-$(CONFIG_REGULATOR_S2MPA01) += s2mpa01.o
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obj-$(CONFIG_REGULATOR_S2MPS11) += s2mps11.o
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obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
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obj-$(CONFIG_REGULATOR_SC2730) += sc2730-regulator.o
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obj-$(CONFIG_REGULATOR_SC2731) += sc2731-regulator.o
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obj-$(CONFIG_REGULATOR_SGM3804) += sgm3804-regulator.o
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obj-$(CONFIG_REGULATOR_SKY81452) += sky81452-regulator.o
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375
drivers/regulator/sc2730-regulator.c
Normal file
375
drivers/regulator/sc2730-regulator.c
Normal file
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@ -0,0 +1,375 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018-2021 Unisoc Inc.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/of_regulator.h>
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/*
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* SC2730 regulator base address
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*/
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#define SC2730_REGULATOR_BASE 0x1800
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/*
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* SC2730 regulator lock register
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*/
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#define SC2730_WR_UNLOCK_VALUE 0x6e7f
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#define SC2730_PWR_WR_PROT (SC2730_REGULATOR_BASE + 0x3d0)
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/*
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* SC2730 enable register
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*/
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#define SC2730_POWER_PD_SW (SC2730_REGULATOR_BASE + 0x01c)
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#define SC2730_LDO_VDDRF18_PD (SC2730_REGULATOR_BASE + 0x10c)
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#define SC2730_LDO_VDDCAMIO_PD (SC2730_REGULATOR_BASE + 0x118)
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#define SC2730_LDO_VDDWCN_PD (SC2730_REGULATOR_BASE + 0x11c)
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#define SC2730_LDO_VDDCAMD1_PD (SC2730_REGULATOR_BASE + 0x128)
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#define SC2730_LDO_VDDCAMD0_PD (SC2730_REGULATOR_BASE + 0x134)
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#define SC2730_LDO_VDDRF1V25_PD (SC2730_REGULATOR_BASE + 0x140)
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#define SC2730_LDO_AVDD12_PD (SC2730_REGULATOR_BASE + 0x14c)
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#define SC2730_LDO_VDDCAMA0_PD (SC2730_REGULATOR_BASE + 0x158)
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#define SC2730_LDO_VDDCAMA1_PD (SC2730_REGULATOR_BASE + 0x164)
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#define SC2730_LDO_VDDCAMMOT_PD (SC2730_REGULATOR_BASE + 0x170)
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#define SC2730_LDO_VDDSIM2_PD (SC2730_REGULATOR_BASE + 0x194)
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#define SC2730_LDO_VDDEMMCCORE_PD (SC2730_REGULATOR_BASE + 0x1a0)
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#define SC2730_LDO_VDDSDCORE_PD (SC2730_REGULATOR_BASE + 0x1ac)
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#define SC2730_LDO_VDDSDIO_PD (SC2730_REGULATOR_BASE + 0x1b8)
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#define SC2730_LDO_VDDWIFIPA_PD (SC2730_REGULATOR_BASE + 0x1d0)
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#define SC2730_LDO_VDDUSB33_PD (SC2730_REGULATOR_BASE + 0x1e8)
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#define SC2730_LDO_VDDLDO0_PD (SC2730_REGULATOR_BASE + 0x1f4)
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#define SC2730_LDO_VDDLDO1_PD (SC2730_REGULATOR_BASE + 0x200)
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#define SC2730_LDO_VDDLDO2_PD (SC2730_REGULATOR_BASE + 0x20c)
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#define SC2730_LDO_VDDKPLED_PD (SC2730_REGULATOR_BASE + 0x38c)
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/*
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* SC2730 enable mask
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*/
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#define SC2730_DCDC_CPU_PD_MASK BIT(4)
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#define SC2730_DCDC_GPU_PD_MASK BIT(3)
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#define SC2730_DCDC_CORE_PD_MASK BIT(5)
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#define SC2730_DCDC_MODEM_PD_MASK BIT(11)
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#define SC2730_DCDC_MEM_PD_MASK BIT(6)
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#define SC2730_DCDC_MEMQ_PD_MASK BIT(12)
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#define SC2730_DCDC_GEN0_PD_MASK BIT(8)
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#define SC2730_DCDC_GEN1_PD_MASK BIT(7)
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#define SC2730_DCDC_SRAM_PD_MASK BIT(13)
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#define SC2730_LDO_AVDD18_PD_MASK BIT(2)
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#define SC2730_LDO_VDDRF18_PD_MASK BIT(0)
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#define SC2730_LDO_VDDCAMIO_PD_MASK BIT(0)
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#define SC2730_LDO_VDDWCN_PD_MASK BIT(0)
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#define SC2730_LDO_VDDCAMD1_PD_MASK BIT(0)
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#define SC2730_LDO_VDDCAMD0_PD_MASK BIT(0)
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#define SC2730_LDO_VDDRF1V25_PD_MASK BIT(0)
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#define SC2730_LDO_AVDD12_PD_MASK BIT(0)
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#define SC2730_LDO_VDDCAMA0_PD_MASK BIT(0)
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#define SC2730_LDO_VDDCAMA1_PD_MASK BIT(0)
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#define SC2730_LDO_VDDCAMMOT_PD_MASK BIT(0)
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#define SC2730_LDO_VDDSIM2_PD_MASK BIT(0)
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#define SC2730_LDO_VDDEMMCCORE_PD_MASK BIT(0)
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#define SC2730_LDO_VDDSDCORE_PD_MASK BIT(0)
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#define SC2730_LDO_VDDSDIO_PD_MASK BIT(0)
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#define SC2730_LDO_VDD28_PD_MASK BIT(1)
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#define SC2730_LDO_VDDWIFIPA_PD_MASK BIT(0)
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#define SC2730_LDO_VDD18_DCXO_PD_MASK BIT(10)
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#define SC2730_LDO_VDDUSB33_PD_MASK BIT(0)
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#define SC2730_LDO_VDDLDO0_PD_MASK BIT(0)
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#define SC2730_LDO_VDDLDO1_PD_MASK BIT(0)
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#define SC2730_LDO_VDDLDO2_PD_MASK BIT(0)
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#define SC2730_LDO_VDDKPLED_PD_MASK BIT(15)
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/*
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* SC2730 vsel register
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*/
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#define SC2730_DCDC_CPU_VOL (SC2730_REGULATOR_BASE + 0x44)
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#define SC2730_DCDC_GPU_VOL (SC2730_REGULATOR_BASE + 0x54)
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#define SC2730_DCDC_CORE_VOL (SC2730_REGULATOR_BASE + 0x64)
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#define SC2730_DCDC_MODEM_VOL (SC2730_REGULATOR_BASE + 0x74)
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#define SC2730_DCDC_MEM_VOL (SC2730_REGULATOR_BASE + 0x84)
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#define SC2730_DCDC_MEMQ_VOL (SC2730_REGULATOR_BASE + 0x94)
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#define SC2730_DCDC_GEN0_VOL (SC2730_REGULATOR_BASE + 0xa4)
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#define SC2730_DCDC_GEN1_VOL (SC2730_REGULATOR_BASE + 0xb4)
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#define SC2730_DCDC_SRAM_VOL (SC2730_REGULATOR_BASE + 0xdc)
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#define SC2730_LDO_AVDD18_VOL (SC2730_REGULATOR_BASE + 0x104)
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#define SC2730_LDO_VDDRF18_VOL (SC2730_REGULATOR_BASE + 0x110)
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#define SC2730_LDO_VDDCAMIO_VOL (SC2730_REGULATOR_BASE + 0x28)
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#define SC2730_LDO_VDDWCN_VOL (SC2730_REGULATOR_BASE + 0x120)
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#define SC2730_LDO_VDDCAMD1_VOL (SC2730_REGULATOR_BASE + 0x12c)
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#define SC2730_LDO_VDDCAMD0_VOL (SC2730_REGULATOR_BASE + 0x138)
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#define SC2730_LDO_VDDRF1V25_VOL (SC2730_REGULATOR_BASE + 0x144)
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#define SC2730_LDO_AVDD12_VOL (SC2730_REGULATOR_BASE + 0x150)
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#define SC2730_LDO_VDDCAMA0_VOL (SC2730_REGULATOR_BASE + 0x15c)
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#define SC2730_LDO_VDDCAMA1_VOL (SC2730_REGULATOR_BASE + 0x168)
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#define SC2730_LDO_VDDCAMMOT_VOL (SC2730_REGULATOR_BASE + 0x174)
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#define SC2730_LDO_VDDSIM2_VOL (SC2730_REGULATOR_BASE + 0x198)
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#define SC2730_LDO_VDDEMMCCORE_VOL (SC2730_REGULATOR_BASE + 0x1a4)
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#define SC2730_LDO_VDDSDCORE_VOL (SC2730_REGULATOR_BASE + 0x1b0)
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#define SC2730_LDO_VDDSDIO_VOL (SC2730_REGULATOR_BASE + 0x1bc)
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#define SC2730_LDO_VDD28_VOL (SC2730_REGULATOR_BASE + 0x1c8)
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#define SC2730_LDO_VDDWIFIPA_VOL (SC2730_REGULATOR_BASE + 0x1d4)
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#define SC2730_LDO_VDD18_DCXO_VOL (SC2730_REGULATOR_BASE + 0x1e0)
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#define SC2730_LDO_VDDUSB33_VOL (SC2730_REGULATOR_BASE + 0x1ec)
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#define SC2730_LDO_VDDLDO0_VOL (SC2730_REGULATOR_BASE + 0x1f8)
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#define SC2730_LDO_VDDLDO1_VOL (SC2730_REGULATOR_BASE + 0x204)
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#define SC2730_LDO_VDDLDO2_VOL (SC2730_REGULATOR_BASE + 0x210)
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#define SC2730_LDO_VDDKPLED_VOL (SC2730_REGULATOR_BASE + 0x38c)
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/*
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* SC2730 vsel register mask
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*/
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#define SC2730_DCDC_CPU_VOL_MASK GENMASK(8, 0)
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#define SC2730_DCDC_GPU_VOL_MASK GENMASK(8, 0)
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#define SC2730_DCDC_CORE_VOL_MASK GENMASK(8, 0)
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#define SC2730_DCDC_MODEM_VOL_MASK GENMASK(8, 0)
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#define SC2730_DCDC_MEM_VOL_MASK GENMASK(7, 0)
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#define SC2730_DCDC_MEMQ_VOL_MASK GENMASK(8, 0)
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#define SC2730_DCDC_GEN0_VOL_MASK GENMASK(7, 0)
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#define SC2730_DCDC_GEN1_VOL_MASK GENMASK(7, 0)
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#define SC2730_DCDC_SRAM_VOL_MASK GENMASK(8, 0)
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#define SC2730_LDO_AVDD18_VOL_MASK GENMASK(5, 0)
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#define SC2730_LDO_VDDRF18_VOL_MASK GENMASK(5, 0)
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#define SC2730_LDO_VDDCAMIO_VOL_MASK GENMASK(5, 0)
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#define SC2730_LDO_VDDWCN_VOL_MASK GENMASK(5, 0)
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#define SC2730_LDO_VDDCAMD1_VOL_MASK GENMASK(4, 0)
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#define SC2730_LDO_VDDCAMD0_VOL_MASK GENMASK(4, 0)
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#define SC2730_LDO_VDDRF1V25_VOL_MASK GENMASK(4, 0)
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#define SC2730_LDO_AVDD12_VOL_MASK GENMASK(4, 0)
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#define SC2730_LDO_VDDCAMA0_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDCAMA1_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDCAMMOT_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDSIM2_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDEMMCCORE_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDSDCORE_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDSDIO_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDD28_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDWIFIPA_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDD18_DCXO_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDUSB33_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDLDO0_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDLDO1_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDLDO2_VOL_MASK GENMASK(7, 0)
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#define SC2730_LDO_VDDKPLED_VOL_MASK GENMASK(14, 7)
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enum sc2730_regulator_id {
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SC2730_DCDC_CPU,
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SC2730_DCDC_GPU,
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SC2730_DCDC_CORE,
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SC2730_DCDC_MODEM,
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SC2730_DCDC_MEM,
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SC2730_DCDC_MEMQ,
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SC2730_DCDC_GEN0,
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SC2730_DCDC_GEN1,
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SC2730_DCDC_SRAM,
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SC2730_LDO_AVDD18,
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SC2730_LDO_VDDRF18,
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SC2730_LDO_VDDCAMIO,
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SC2730_LDO_VDDWCN,
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SC2730_LDO_VDDCAMD1,
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SC2730_LDO_VDDCAMD0,
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SC2730_LDO_VDDRF1V25,
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SC2730_LDO_AVDD12,
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SC2730_LDO_VDDCAMA0,
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SC2730_LDO_VDDCAMA1,
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SC2730_LDO_VDDCAMMOT,
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SC2730_LDO_VDDSIM2,
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SC2730_LDO_VDDEMMCCORE,
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SC2730_LDO_VDDSDCORE,
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SC2730_LDO_VDDSDIO,
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SC2730_LDO_VDD28,
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SC2730_LDO_VDDWIFIPA,
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SC2730_LDO_VDD18_DCXO,
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SC2730_LDO_VDDUSB33,
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SC2730_LDO_VDDLDO0,
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SC2730_LDO_VDDLDO1,
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SC2730_LDO_VDDLDO2,
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SC2730_LDO_VDDKPLED,
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};
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static const struct regulator_ops sc2730_regu_linear_ops = {
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.enable = regulator_enable_regmap,
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.disable = regulator_disable_regmap,
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.is_enabled = regulator_is_enabled_regmap,
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.list_voltage = regulator_list_voltage_linear,
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.get_voltage_sel = regulator_get_voltage_sel_regmap,
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.set_voltage_sel = regulator_set_voltage_sel_regmap,
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};
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#define SC2730_REGU_LINEAR(_id, of_name, en_reg, en_mask, vreg, vmask, \
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vstep, vmin, vmax) { \
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.name = #_id, \
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.of_match = of_name, \
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.regulators_node = "regulators", \
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.ops = &sc2730_regu_linear_ops, \
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.type = REGULATOR_VOLTAGE, \
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.id = SC2730_##_id, \
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.owner = THIS_MODULE, \
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.min_uV = vmin, \
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.n_voltages = ((vmax) - (vmin)) / (vstep) + 1, \
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.uV_step = vstep, \
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.enable_is_inverted = true, \
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.enable_val = 0, \
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.enable_reg = en_reg, \
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.enable_mask = en_mask, \
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.vsel_reg = vreg, \
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.vsel_mask = vmask, \
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.linear_min_sel = 0, \
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}
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static const struct regulator_desc regulators[] = {
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SC2730_REGU_LINEAR(DCDC_CPU, "dcdc-cpu", SC2730_POWER_PD_SW,
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SC2730_DCDC_CPU_PD_MASK, SC2730_DCDC_CPU_VOL,
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SC2730_DCDC_CPU_VOL_MASK, 3125, 0, 1596875),
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SC2730_REGU_LINEAR(DCDC_GPU, "dcdc-gpu", SC2730_POWER_PD_SW,
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SC2730_DCDC_GPU_PD_MASK, SC2730_DCDC_GPU_VOL,
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SC2730_DCDC_GPU_VOL_MASK, 3125, 0, 1596875),
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SC2730_REGU_LINEAR(DCDC_CORE, "dcdc-core", SC2730_POWER_PD_SW,
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SC2730_DCDC_CORE_PD_MASK, SC2730_DCDC_CORE_VOL,
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SC2730_DCDC_CORE_VOL_MASK, 3125, 0, 1596875),
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SC2730_REGU_LINEAR(DCDC_MODEM, "dcdc-modem", SC2730_POWER_PD_SW,
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SC2730_DCDC_MODEM_PD_MASK, SC2730_DCDC_MODEM_VOL,
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SC2730_DCDC_MODEM_VOL_MASK, 3125, 0, 1596875),
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SC2730_REGU_LINEAR(DCDC_MEM, "dcdc-mem", SC2730_POWER_PD_SW,
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SC2730_DCDC_MEM_PD_MASK, SC2730_DCDC_MEM_VOL,
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SC2730_DCDC_MEM_VOL_MASK, 6250, 0, 1593750),
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SC2730_REGU_LINEAR(DCDC_MEMQ, "dcdc-memq", SC2730_POWER_PD_SW,
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SC2730_DCDC_MEMQ_PD_MASK, SC2730_DCDC_MEMQ_VOL,
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SC2730_DCDC_MEMQ_VOL_MASK, 3125, 0, 1596875),
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SC2730_REGU_LINEAR(DCDC_GEN0, "dcdc-gen0", SC2730_POWER_PD_SW,
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SC2730_DCDC_GEN0_PD_MASK, SC2730_DCDC_GEN0_VOL,
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SC2730_DCDC_GEN0_VOL_MASK, 9375, 20000, 2410625),
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SC2730_REGU_LINEAR(DCDC_GEN1, "dcdc-gen1", SC2730_POWER_PD_SW,
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SC2730_DCDC_GEN1_PD_MASK, SC2730_DCDC_GEN1_VOL,
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SC2730_DCDC_GEN1_VOL_MASK, 6250, 50000, 1643750),
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SC2730_REGU_LINEAR(DCDC_SRAM, "dcdc-sram", SC2730_POWER_PD_SW,
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SC2730_DCDC_SRAM_PD_MASK, SC2730_DCDC_SRAM_VOL,
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SC2730_DCDC_SRAM_VOL_MASK, 3125, 0, 1596875),
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SC2730_REGU_LINEAR(LDO_AVDD18, "ldo-avdd18", SC2730_POWER_PD_SW,
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SC2730_LDO_AVDD18_PD_MASK, SC2730_LDO_AVDD18_VOL,
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SC2730_LDO_AVDD18_VOL_MASK, 10000, 1175000, 1805000),
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SC2730_REGU_LINEAR(LDO_VDDRF18, "ldo-vddrf18", SC2730_LDO_VDDRF18_PD,
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SC2730_LDO_VDDRF18_PD_MASK, SC2730_LDO_VDDRF18_VOL,
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SC2730_LDO_VDDRF18_VOL_MASK, 10000, 1175000, 1805000),
|
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SC2730_REGU_LINEAR(LDO_VDDCAMIO, "ldo-vddcamio", SC2730_LDO_VDDCAMIO_PD,
|
||||
SC2730_LDO_VDDCAMIO_PD_MASK, SC2730_LDO_VDDCAMIO_VOL,
|
||||
SC2730_LDO_VDDCAMIO_VOL_MASK, 10000, 1200000, 1830000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDWCN, "ldo-vddwcn", SC2730_LDO_VDDWCN_PD,
|
||||
SC2730_LDO_VDDWCN_PD_MASK, SC2730_LDO_VDDWCN_VOL,
|
||||
SC2730_LDO_VDDWCN_VOL_MASK, 15000, 900000, 1845000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDCAMD1, "ldo-vddcamd1", SC2730_LDO_VDDCAMD1_PD,
|
||||
SC2730_LDO_VDDCAMD1_PD_MASK, SC2730_LDO_VDDCAMD1_VOL,
|
||||
SC2730_LDO_VDDCAMD1_VOL_MASK, 15000, 900000, 1365000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDCAMD0, "ldo-vddcamd0", SC2730_LDO_VDDCAMD0_PD,
|
||||
SC2730_LDO_VDDCAMD0_PD_MASK, SC2730_LDO_VDDCAMD0_VOL,
|
||||
SC2730_LDO_VDDCAMD0_VOL_MASK, 15000, 900000, 1365000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDRF1V25, "ldo-vddrf1v25", SC2730_LDO_VDDRF1V25_PD,
|
||||
SC2730_LDO_VDDRF1V25_PD_MASK, SC2730_LDO_VDDRF1V25_VOL,
|
||||
SC2730_LDO_VDDRF1V25_VOL_MASK, 15000, 900000, 1365000),
|
||||
SC2730_REGU_LINEAR(LDO_AVDD12, "ldo-avdd12", SC2730_LDO_AVDD12_PD,
|
||||
SC2730_LDO_AVDD12_PD_MASK, SC2730_LDO_AVDD12_VOL,
|
||||
SC2730_LDO_AVDD12_VOL_MASK, 15000, 900000, 1365000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDCAMA0, "ldo-vddcama0", SC2730_LDO_VDDCAMA0_PD,
|
||||
SC2730_LDO_VDDCAMA0_PD_MASK, SC2730_LDO_VDDCAMA0_VOL,
|
||||
SC2730_LDO_VDDCAMA0_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDCAMA1, "ldo-vddcama1", SC2730_LDO_VDDCAMA1_PD,
|
||||
SC2730_LDO_VDDCAMA1_PD_MASK, SC2730_LDO_VDDCAMA1_VOL,
|
||||
SC2730_LDO_VDDCAMA1_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDCAMMOT, "ldo-vddcammot", SC2730_LDO_VDDCAMMOT_PD,
|
||||
SC2730_LDO_VDDCAMMOT_PD_MASK, SC2730_LDO_VDDCAMMOT_VOL,
|
||||
SC2730_LDO_VDDCAMMOT_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDSIM2, "ldo-vddsim2", SC2730_LDO_VDDSIM2_PD,
|
||||
SC2730_LDO_VDDSIM2_PD_MASK, SC2730_LDO_VDDSIM2_VOL,
|
||||
SC2730_LDO_VDDSIM2_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDEMMCCORE, "ldo-vddemmccore", SC2730_LDO_VDDEMMCCORE_PD,
|
||||
SC2730_LDO_VDDEMMCCORE_PD_MASK, SC2730_LDO_VDDEMMCCORE_VOL,
|
||||
SC2730_LDO_VDDEMMCCORE_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDSDCORE, "ldo-vddsdcore", SC2730_LDO_VDDSDCORE_PD,
|
||||
SC2730_LDO_VDDSDCORE_PD_MASK, SC2730_LDO_VDDSDCORE_VOL,
|
||||
SC2730_LDO_VDDSDCORE_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDSDIO, "ldo-vddsdio", SC2730_LDO_VDDSDIO_PD,
|
||||
SC2730_LDO_VDDSDIO_PD_MASK, SC2730_LDO_VDDSDIO_VOL,
|
||||
SC2730_LDO_VDDSDIO_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDD28, "ldo-vdd28", SC2730_POWER_PD_SW,
|
||||
SC2730_LDO_VDD28_PD_MASK, SC2730_LDO_VDD28_VOL,
|
||||
SC2730_LDO_VDD28_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDWIFIPA, "ldo-vddwifipa", SC2730_LDO_VDDWIFIPA_PD,
|
||||
SC2730_LDO_VDDWIFIPA_PD_MASK, SC2730_LDO_VDDWIFIPA_VOL,
|
||||
SC2730_LDO_VDDWIFIPA_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDD18_DCXO, "ldo-vdd18-dcxo", SC2730_POWER_PD_SW,
|
||||
SC2730_LDO_VDD18_DCXO_PD_MASK, SC2730_LDO_VDD18_DCXO_VOL,
|
||||
SC2730_LDO_VDD18_DCXO_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDUSB33, "ldo-vddusb33", SC2730_LDO_VDDUSB33_PD,
|
||||
SC2730_LDO_VDDUSB33_PD_MASK, SC2730_LDO_VDDUSB33_VOL,
|
||||
SC2730_LDO_VDDUSB33_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDLDO0, "ldo-vddldo0", SC2730_LDO_VDDLDO0_PD,
|
||||
SC2730_LDO_VDDLDO0_PD_MASK, SC2730_LDO_VDDLDO0_VOL,
|
||||
SC2730_LDO_VDDLDO0_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDLDO1, "ldo-vddldo1", SC2730_LDO_VDDLDO1_PD,
|
||||
SC2730_LDO_VDDLDO1_PD_MASK, SC2730_LDO_VDDLDO1_VOL,
|
||||
SC2730_LDO_VDDLDO1_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDLDO2, "ldo-vddldo2", SC2730_LDO_VDDLDO2_PD,
|
||||
SC2730_LDO_VDDLDO2_PD_MASK, SC2730_LDO_VDDLDO2_VOL,
|
||||
SC2730_LDO_VDDLDO2_VOL_MASK, 10000, 1200000, 3750000),
|
||||
SC2730_REGU_LINEAR(LDO_VDDKPLED, "ldo-vddkpled", SC2730_LDO_VDDKPLED_PD,
|
||||
SC2730_LDO_VDDKPLED_PD_MASK, SC2730_LDO_VDDKPLED_VOL,
|
||||
SC2730_LDO_VDDKPLED_VOL_MASK, 10000, 1200000, 3750000),
|
||||
};
|
||||
|
||||
static int sc2730_regulator_unlock(struct regmap *regmap)
|
||||
{
|
||||
return regmap_write(regmap, SC2730_PWR_WR_PROT, SC2730_WR_UNLOCK_VALUE);
|
||||
}
|
||||
|
||||
static int sc2730_regulator_probe(struct platform_device *pdev)
|
||||
{
|
||||
int i, ret;
|
||||
struct regmap *regmap;
|
||||
struct regulator_config config = { };
|
||||
struct regulator_dev *rdev;
|
||||
|
||||
regmap = dev_get_regmap(pdev->dev.parent, NULL);
|
||||
if (!regmap)
|
||||
return dev_err_probe(&pdev->dev, -ENODEV, "failed to get regmap\n");
|
||||
|
||||
ret = sc2730_regulator_unlock(regmap);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret, "failed to release regulator lock\n");
|
||||
|
||||
config.dev = pdev->dev.parent;
|
||||
config.regmap = regmap;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(regulators); i++) {
|
||||
rdev = devm_regulator_register(&pdev->dev, ®ulators[i], &config);
|
||||
if (IS_ERR(rdev)) {
|
||||
return dev_err_probe(&pdev->dev, PTR_ERR(rdev),
|
||||
"failed to register regulator %s\n",
|
||||
regulators[i].name);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_device_id sc2730_regulator_id_table[] = {
|
||||
{ .name = "sc2730-regulator" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, sc2730_regulator_id_table);
|
||||
|
||||
static struct platform_driver sc2730_regulator_driver = {
|
||||
.driver = {
|
||||
.name = "sc2730-regulator",
|
||||
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
|
||||
},
|
||||
.probe = sc2730_regulator_probe,
|
||||
.id_table = sc2730_regulator_id_table,
|
||||
};
|
||||
|
||||
module_platform_driver(sc2730_regulator_driver);
|
||||
|
||||
MODULE_AUTHOR("Zhongfa Wang <zhongfa.wang@unisoc.com>");
|
||||
MODULE_DESCRIPTION("Spreadtrum SC2730 regulator driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user