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arm64: dts: st: add eth1 pins for stm32mp2x platforms

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Eth1 ethernet controller is present on every stm32mp2x vendor boards.
Describe the pinctrl of eth1 for each of them.

Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Link: https://lore.kernel.org/r/20250904-mp2_ethernet-v2-1-05a060157fb7@foss.st.com
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Gatien Chevallier 2025-09-04 09:40:56 +02:00 committed by Alexandre Torgue
parent bd0c7718ae
commit 4c2ac7b9ab
1 changed files with 126 additions and 0 deletions
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126
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
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@ -6,6 +6,132 @@
#include <dt-bindings/pinctrl/stm32-pinfunc.h>
&pinctrl {
eth1_mdio_pins_a: eth1-mdio-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */
bias-disable;
drive-push-pull;
slew-rate = <2>;
};
pins2 {
pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
};
eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 {
pins1 {
pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */
};
};
eth1_rgmii_pins_a: eth1-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins3 {
pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 {
pins {
pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */
};
};
eth1_rgmii_pins_b: eth1-rgmii-1 {
pins1 {
pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins2 {
pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */
<STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
pins3 {
pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */
bias-disable;
};
pins4 {
pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
bias-disable;
};
};
eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 {
pins {
pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */
<STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */
<STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */
<STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */
<STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */
<STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */
<STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */
<STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */
<STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */
<STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */
<STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */
<STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */
<STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */
<STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */
<STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */
};
};
eth2_rgmii_pins_a: eth2-rgmii-0 {
pins1 {
pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */