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arm64: dts: qcom: sm8650: add the missing l2 cache node

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Only two little a520s share the same L2, every a720 has their own L2
cache.

Fixes: d235037799 ("arm64: dts: qcom: add initial SM8650 dtsi")
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250405105529.309711-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Pengyu Luo 2025-04-05 18:55:28 +08:00 committed by Bjorn Andersson
parent d12fbd11c5
commit 4becd72352
1 changed files with 8 additions and 1 deletions
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9
arch/arm64/boot/dts/qcom/sm8650.dtsi
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@ -188,7 +188,7 @@ cpu3: cpu@300 {
power-domain-names = "psci";
enable-method = "psci";
next-level-cache = <&l2_200>;
next-level-cache = <&l2_300>;
capacity-dmips-mhz = <1792>;
dynamic-power-coefficient = <238>;
@ -204,6 +204,13 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_0>;
};
};
cpu4: cpu@400 {