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arm64: dts: qcom: lemans: Add eDP ref clock for eDP PHYs

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The eDP PHY nodes on lemans were missing the reference clock voting.
This initially went unnoticed because the clock was implicitly enabled
by the UFS PHY driver, and the eDP PHY happened to rely on that.

After commit 77d2fa54a9 ("scsi: ufs: qcom : Refactor phy_power_on/off
calls"), the UFS driver no longer keeps the reference clock enabled.
As a result, the eDP PHY fails to power on.

To fix this, add eDP reference clock for eDP PHYs on lemans chipset
ensuring reference clock is enabled.

Fixes: e1e3e5673f ("arm64: dts: qcom: sa8775p: add DisplayPort device nodes")
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260128114853.2543416-3-quic_riteshk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Ritesh Kumar 2026-01-28 17:18:50 +05:30 committed by Bjorn Andersson
parent 2c7e6d4264
commit 4bd073e00f
1 changed files with 8 additions and 4 deletions
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12
arch/arm64/boot/dts/qcom/lemans.dtsi
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@ -5658,9 +5658,11 @@ mdss0_dp0_phy: phy@aec2a00 {
<0x0 0x0aec2000 0x0 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_EDP_REF_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb";
"cfg_ahb",
"ref";
#clock-cells = <1>;
#phy-cells = <0>;
@ -5677,9 +5679,11 @@ mdss0_dp1_phy: phy@aec5a00 {
<0x0 0x0aec5000 0x0 0x1c8>;
clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK>,
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>;
<&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_EDP_REF_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb";
"cfg_ahb",
"ref";
#clock-cells = <1>;
#phy-cells = <0>;