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Merge branch kvm-arm64/mmio-sea into kvmarm/next
* kvm-arm64/mmio-sea: : Fix for SEA injection in response to MMIO : : Fix + test coverage for SEA injection in response to an unhandled MMIO : exit to userspace. Naturally, if userspace decides to abort an MMIO : instruction KVM shouldn't continue with instruction emulation... KVM: arm64: selftests: Add tests for MMIO external abort injection KVM: arm64: selftests: Convert to kernel's ESR terminology tools: arm64: Grab a copy of esr.h from kernel KVM: arm64: Don't retire aborted MMIO instruction Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
This commit is contained in:
Oliver Upton
commit
4bc1a8808e
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@ -72,6 +72,31 @@ unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len)
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return data;
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}
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static bool kvm_pending_sync_exception(struct kvm_vcpu *vcpu)
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{
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if (!vcpu_get_flag(vcpu, PENDING_EXCEPTION))
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return false;
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if (vcpu_el1_is_32bit(vcpu)) {
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switch (vcpu_get_flag(vcpu, EXCEPT_MASK)) {
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case unpack_vcpu_flag(EXCEPT_AA32_UND):
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case unpack_vcpu_flag(EXCEPT_AA32_IABT):
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case unpack_vcpu_flag(EXCEPT_AA32_DABT):
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return true;
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default:
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return false;
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}
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} else {
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switch (vcpu_get_flag(vcpu, EXCEPT_MASK)) {
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case unpack_vcpu_flag(EXCEPT_AA64_EL1_SYNC):
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case unpack_vcpu_flag(EXCEPT_AA64_EL2_SYNC):
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return true;
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default:
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return false;
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}
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}
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}
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/**
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* kvm_handle_mmio_return -- Handle MMIO loads after user space emulation
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* or in-kernel IO emulation
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@ -84,8 +109,11 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu)
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unsigned int len;
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int mask;
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/* Detect an already handled MMIO return */
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if (unlikely(!vcpu->mmio_needed))
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/*
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* Detect if the MMIO return was already handled or if userspace aborted
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* the MMIO access.
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*/
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if (unlikely(!vcpu->mmio_needed || kvm_pending_sync_exception(vcpu)))
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return 1;
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vcpu->mmio_needed = 0;
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42
tools/arch/arm64/include/asm/brk-imm.h
Normal file
42
tools/arch/arm64/include/asm/brk-imm.h
Normal file
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@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 ARM Ltd.
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*/
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#ifndef __ASM_BRK_IMM_H
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#define __ASM_BRK_IMM_H
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/*
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* #imm16 values used for BRK instruction generation
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* 0x004: for installing kprobes
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* 0x005: for installing uprobes
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* 0x006: for kprobe software single-step
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* 0x007: for kretprobe return
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* Allowed values for kgdb are 0x400 - 0x7ff
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* 0x100: for triggering a fault on purpose (reserved)
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* 0x400: for dynamic BRK instruction
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* 0x401: for compile time BRK instruction
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* 0x800: kernel-mode BUG() and WARN() traps
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* 0x9xx: tag-based KASAN trap (allowed values 0x900 - 0x9ff)
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* 0x55xx: Undefined Behavior Sanitizer traps ('U' << 8)
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* 0x8xxx: Control-Flow Integrity traps
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*/
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#define KPROBES_BRK_IMM 0x004
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#define UPROBES_BRK_IMM 0x005
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#define KPROBES_BRK_SS_IMM 0x006
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#define KRETPROBES_BRK_IMM 0x007
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#define FAULT_BRK_IMM 0x100
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#define KGDB_DYN_DBG_BRK_IMM 0x400
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#define KGDB_COMPILED_DBG_BRK_IMM 0x401
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#define BUG_BRK_IMM 0x800
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#define KASAN_BRK_IMM 0x900
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#define KASAN_BRK_MASK 0x0ff
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#define UBSAN_BRK_IMM 0x5500
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#define UBSAN_BRK_MASK 0x00ff
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#define CFI_BRK_IMM_TARGET GENMASK(4, 0)
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#define CFI_BRK_IMM_TYPE GENMASK(9, 5)
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#define CFI_BRK_IMM_BASE 0x8000
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#define CFI_BRK_IMM_MASK (CFI_BRK_IMM_TARGET | CFI_BRK_IMM_TYPE)
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#endif
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455
tools/arch/arm64/include/asm/esr.h
Normal file
455
tools/arch/arm64/include/asm/esr.h
Normal file
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@ -0,0 +1,455 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#ifndef __ASM_ESR_H
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#define __ASM_ESR_H
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#include <asm/sysreg.h>
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#define ESR_ELx_EC_UNKNOWN UL(0x00)
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#define ESR_ELx_EC_WFx UL(0x01)
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/* Unallocated EC: 0x02 */
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#define ESR_ELx_EC_CP15_32 UL(0x03)
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#define ESR_ELx_EC_CP15_64 UL(0x04)
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#define ESR_ELx_EC_CP14_MR UL(0x05)
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#define ESR_ELx_EC_CP14_LS UL(0x06)
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#define ESR_ELx_EC_FP_ASIMD UL(0x07)
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#define ESR_ELx_EC_CP10_ID UL(0x08) /* EL2 only */
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#define ESR_ELx_EC_PAC UL(0x09) /* EL2 and above */
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/* Unallocated EC: 0x0A - 0x0B */
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#define ESR_ELx_EC_CP14_64 UL(0x0C)
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#define ESR_ELx_EC_BTI UL(0x0D)
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#define ESR_ELx_EC_ILL UL(0x0E)
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/* Unallocated EC: 0x0F - 0x10 */
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#define ESR_ELx_EC_SVC32 UL(0x11)
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#define ESR_ELx_EC_HVC32 UL(0x12) /* EL2 only */
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#define ESR_ELx_EC_SMC32 UL(0x13) /* EL2 and above */
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/* Unallocated EC: 0x14 */
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#define ESR_ELx_EC_SVC64 UL(0x15)
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#define ESR_ELx_EC_HVC64 UL(0x16) /* EL2 and above */
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#define ESR_ELx_EC_SMC64 UL(0x17) /* EL2 and above */
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#define ESR_ELx_EC_SYS64 UL(0x18)
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#define ESR_ELx_EC_SVE UL(0x19)
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#define ESR_ELx_EC_ERET UL(0x1a) /* EL2 only */
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/* Unallocated EC: 0x1B */
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#define ESR_ELx_EC_FPAC UL(0x1C) /* EL1 and above */
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#define ESR_ELx_EC_SME UL(0x1D)
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/* Unallocated EC: 0x1E */
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#define ESR_ELx_EC_IMP_DEF UL(0x1f) /* EL3 only */
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#define ESR_ELx_EC_IABT_LOW UL(0x20)
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#define ESR_ELx_EC_IABT_CUR UL(0x21)
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#define ESR_ELx_EC_PC_ALIGN UL(0x22)
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/* Unallocated EC: 0x23 */
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#define ESR_ELx_EC_DABT_LOW UL(0x24)
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#define ESR_ELx_EC_DABT_CUR UL(0x25)
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#define ESR_ELx_EC_SP_ALIGN UL(0x26)
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#define ESR_ELx_EC_MOPS UL(0x27)
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#define ESR_ELx_EC_FP_EXC32 UL(0x28)
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/* Unallocated EC: 0x29 - 0x2B */
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#define ESR_ELx_EC_FP_EXC64 UL(0x2C)
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/* Unallocated EC: 0x2D - 0x2E */
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#define ESR_ELx_EC_SERROR UL(0x2F)
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#define ESR_ELx_EC_BREAKPT_LOW UL(0x30)
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#define ESR_ELx_EC_BREAKPT_CUR UL(0x31)
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#define ESR_ELx_EC_SOFTSTP_LOW UL(0x32)
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#define ESR_ELx_EC_SOFTSTP_CUR UL(0x33)
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#define ESR_ELx_EC_WATCHPT_LOW UL(0x34)
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#define ESR_ELx_EC_WATCHPT_CUR UL(0x35)
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/* Unallocated EC: 0x36 - 0x37 */
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#define ESR_ELx_EC_BKPT32 UL(0x38)
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/* Unallocated EC: 0x39 */
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#define ESR_ELx_EC_VECTOR32 UL(0x3A) /* EL2 only */
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/* Unallocated EC: 0x3B */
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#define ESR_ELx_EC_BRK64 UL(0x3C)
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/* Unallocated EC: 0x3D - 0x3F */
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#define ESR_ELx_EC_MAX UL(0x3F)
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#define ESR_ELx_EC_SHIFT (26)
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#define ESR_ELx_EC_WIDTH (6)
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#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
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#define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
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#define ESR_ELx_IL_SHIFT (25)
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#define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
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#define ESR_ELx_ISS_MASK (GENMASK(24, 0))
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#define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK)
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#define ESR_ELx_ISS2_SHIFT (32)
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#define ESR_ELx_ISS2_MASK (GENMASK_ULL(55, 32))
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#define ESR_ELx_ISS2(esr) (((esr) & ESR_ELx_ISS2_MASK) >> ESR_ELx_ISS2_SHIFT)
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/* ISS field definitions shared by different classes */
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#define ESR_ELx_WNR_SHIFT (6)
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#define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
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/* Asynchronous Error Type */
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#define ESR_ELx_IDS_SHIFT (24)
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#define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
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#define ESR_ELx_AET_SHIFT (10)
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#define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
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#define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
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/* Shared ISS field definitions for Data/Instruction aborts */
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#define ESR_ELx_SET_SHIFT (11)
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#define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
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#define ESR_ELx_FnV_SHIFT (10)
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#define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
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#define ESR_ELx_EA_SHIFT (9)
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#define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
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#define ESR_ELx_S1PTW_SHIFT (7)
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#define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
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/* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
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#define ESR_ELx_FSC (0x3F)
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#define ESR_ELx_FSC_TYPE (0x3C)
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#define ESR_ELx_FSC_LEVEL (0x03)
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#define ESR_ELx_FSC_EXTABT (0x10)
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#define ESR_ELx_FSC_MTE (0x11)
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#define ESR_ELx_FSC_SERROR (0x11)
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#define ESR_ELx_FSC_ACCESS (0x08)
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#define ESR_ELx_FSC_FAULT (0x04)
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#define ESR_ELx_FSC_PERM (0x0C)
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#define ESR_ELx_FSC_SEA_TTW(n) (0x14 + (n))
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#define ESR_ELx_FSC_SECC (0x18)
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#define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))
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/* Status codes for individual page table levels */
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#define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + (n))
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#define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + (n))
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#define ESR_ELx_FSC_FAULT_nL (0x2C)
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#define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
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ESR_ELx_FSC_FAULT) + (n))
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/* ISS field definitions for Data Aborts */
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#define ESR_ELx_ISV_SHIFT (24)
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#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
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#define ESR_ELx_SAS_SHIFT (22)
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#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
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#define ESR_ELx_SSE_SHIFT (21)
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#define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
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#define ESR_ELx_SRT_SHIFT (16)
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#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
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#define ESR_ELx_SF_SHIFT (15)
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#define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
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#define ESR_ELx_AR_SHIFT (14)
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#define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
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#define ESR_ELx_CM_SHIFT (8)
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#define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
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/* ISS2 field definitions for Data Aborts */
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#define ESR_ELx_TnD_SHIFT (10)
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#define ESR_ELx_TnD (UL(1) << ESR_ELx_TnD_SHIFT)
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#define ESR_ELx_TagAccess_SHIFT (9)
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#define ESR_ELx_TagAccess (UL(1) << ESR_ELx_TagAccess_SHIFT)
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#define ESR_ELx_GCS_SHIFT (8)
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#define ESR_ELx_GCS (UL(1) << ESR_ELx_GCS_SHIFT)
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#define ESR_ELx_Overlay_SHIFT (6)
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#define ESR_ELx_Overlay (UL(1) << ESR_ELx_Overlay_SHIFT)
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#define ESR_ELx_DirtyBit_SHIFT (5)
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#define ESR_ELx_DirtyBit (UL(1) << ESR_ELx_DirtyBit_SHIFT)
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#define ESR_ELx_Xs_SHIFT (0)
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#define ESR_ELx_Xs_MASK (GENMASK_ULL(4, 0))
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|
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/* ISS field definitions for exceptions taken in to Hyp */
|
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#define ESR_ELx_FSC_ADDRSZ (0x00)
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#define ESR_ELx_FSC_ADDRSZ_L(n) (ESR_ELx_FSC_ADDRSZ + (n))
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#define ESR_ELx_CV (UL(1) << 24)
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#define ESR_ELx_COND_SHIFT (20)
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#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
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#define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5)
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#define ESR_ELx_WFx_ISS_RV (UL(1) << 2)
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#define ESR_ELx_WFx_ISS_TI (UL(3) << 0)
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#define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0)
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#define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
|
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#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
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#define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1)
|
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|
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#define DISR_EL1_IDS (UL(1) << 24)
|
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/*
|
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* DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
|
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* different things in the future...
|
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*/
|
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#define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
|
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|
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/* ESR value templates for specific events */
|
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#define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \
|
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(ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT))
|
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#define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
|
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ESR_ELx_WFx_ISS_WFI)
|
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|
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/* BRK instruction trap from AArch64 state */
|
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#define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
|
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|
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/* ISS field definitions for System instruction traps */
|
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#define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
|
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#define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
|
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#define ESR_ELx_SYS64_ISS_DIR_READ 0x1
|
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#define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
|
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|
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#define ESR_ELx_SYS64_ISS_RT_SHIFT 5
|
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#define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
|
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#define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
|
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#define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
|
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#define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
|
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#define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
|
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#define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
|
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#define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
|
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ESR_ELx_SYS64_ISS_OP1_MASK | \
|
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ESR_ELx_SYS64_ISS_OP2_MASK | \
|
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ESR_ELx_SYS64_ISS_CRN_MASK | \
|
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ESR_ELx_SYS64_ISS_CRM_MASK)
|
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#define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
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(((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
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((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
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((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
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((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
|
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((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
|
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|
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#define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
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ESR_ELx_SYS64_ISS_DIR_MASK)
|
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#define ESR_ELx_SYS64_ISS_RT(esr) \
|
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(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
|
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/*
|
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* User space cache operations have the following sysreg encoding
|
||||
* in System instructions.
|
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* op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
|
||||
*/
|
||||
#define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
|
||||
#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
|
||||
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
|
||||
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
|
||||
#define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
|
||||
#define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
|
||||
|
||||
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
|
||||
ESR_ELx_SYS64_ISS_OP1_MASK | \
|
||||
ESR_ELx_SYS64_ISS_OP2_MASK | \
|
||||
ESR_ELx_SYS64_ISS_CRN_MASK | \
|
||||
ESR_ELx_SYS64_ISS_DIR_MASK)
|
||||
#define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
|
||||
(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_WRITE)
|
||||
/*
|
||||
* User space MRS operations which are supported for emulation
|
||||
* have the following sysreg encoding in System instructions.
|
||||
* op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
|
||||
*/
|
||||
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
|
||||
ESR_ELx_SYS64_ISS_OP1_MASK | \
|
||||
ESR_ELx_SYS64_ISS_CRN_MASK | \
|
||||
ESR_ELx_SYS64_ISS_DIR_MASK)
|
||||
#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
|
||||
(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
|
||||
ESR_ELx_SYS64_ISS_DIR_READ)
|
||||
|
||||
#define esr_sys64_to_sysreg(e) \
|
||||
sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_OP0_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_OP1_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_CRN_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_CRM_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_OP2_SHIFT))
|
||||
|
||||
#define esr_cp15_to_sysreg(e) \
|
||||
sys_reg(3, \
|
||||
(((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_OP1_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_CRN_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_CRM_SHIFT), \
|
||||
(((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
|
||||
ESR_ELx_SYS64_ISS_OP2_SHIFT))
|
||||
|
||||
/* ISS field definitions for ERET/ERETAA/ERETAB trapping */
|
||||
#define ESR_ELx_ERET_ISS_ERET 0x2
|
||||
#define ESR_ELx_ERET_ISS_ERETA 0x1
|
||||
|
||||
/*
|
||||
* ISS field definitions for floating-point exception traps
|
||||
* (FP_EXC_32/FP_EXC_64).
|
||||
*
|
||||
* (The FPEXC_* constants are used instead for common bits.)
|
||||
*/
|
||||
|
||||
#define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
|
||||
|
||||
/*
|
||||
* ISS field definitions for CP15 accesses
|
||||
*/
|
||||
#define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
|
||||
#define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
|
||||
#define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
|
||||
|
||||
#define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
|
||||
#define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
|
||||
#define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
|
||||
#define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
|
||||
#define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
|
||||
#define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
|
||||
#define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
|
||||
#define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
|
||||
#define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
|
||||
#define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
|
||||
|
||||
#define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
|
||||
ESR_ELx_CP15_32_ISS_OP2_MASK | \
|
||||
ESR_ELx_CP15_32_ISS_CRN_MASK | \
|
||||
ESR_ELx_CP15_32_ISS_CRM_MASK | \
|
||||
ESR_ELx_CP15_32_ISS_DIR_MASK)
|
||||
#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
|
||||
(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
|
||||
((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
|
||||
((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
|
||||
((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
|
||||
#define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
|
||||
#define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
|
||||
#define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
|
||||
#define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
|
||||
#define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
|
||||
#define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
|
||||
#define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
|
||||
(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
|
||||
((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
|
||||
ESR_ELx_CP15_64_ISS_CRM_MASK | \
|
||||
ESR_ELx_CP15_64_ISS_DIR_MASK)
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
|
||||
ESR_ELx_CP15_64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \
|
||||
ESR_ELx_CP15_64_ISS_DIR_READ)
|
||||
|
||||
#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
|
||||
ESR_ELx_CP15_32_ISS_DIR_READ)
|
||||
|
||||
/*
|
||||
* ISS values for SME traps
|
||||
*/
|
||||
|
||||
#define ESR_ELx_SME_ISS_SME_DISABLED 0
|
||||
#define ESR_ELx_SME_ISS_ILL 1
|
||||
#define ESR_ELx_SME_ISS_SM_DISABLED 2
|
||||
#define ESR_ELx_SME_ISS_ZA_DISABLED 3
|
||||
#define ESR_ELx_SME_ISS_ZT_DISABLED 4
|
||||
|
||||
/* ISS field definitions for MOPS exceptions */
|
||||
#define ESR_ELx_MOPS_ISS_MEM_INST (UL(1) << 24)
|
||||
#define ESR_ELx_MOPS_ISS_FROM_EPILOGUE (UL(1) << 18)
|
||||
#define ESR_ELx_MOPS_ISS_WRONG_OPTION (UL(1) << 17)
|
||||
#define ESR_ELx_MOPS_ISS_OPTION_A (UL(1) << 16)
|
||||
#define ESR_ELx_MOPS_ISS_DESTREG(esr) (((esr) & (UL(0x1f) << 10)) >> 10)
|
||||
#define ESR_ELx_MOPS_ISS_SRCREG(esr) (((esr) & (UL(0x1f) << 5)) >> 5)
|
||||
#define ESR_ELx_MOPS_ISS_SIZEREG(esr) (((esr) & (UL(0x1f) << 0)) >> 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/types.h>
|
||||
|
||||
static inline unsigned long esr_brk_comment(unsigned long esr)
|
||||
{
|
||||
return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;
|
||||
}
|
||||
|
||||
static inline bool esr_is_data_abort(unsigned long esr)
|
||||
{
|
||||
const unsigned long ec = ESR_ELx_EC(esr);
|
||||
|
||||
return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
|
||||
}
|
||||
|
||||
static inline bool esr_is_cfi_brk(unsigned long esr)
|
||||
{
|
||||
return ESR_ELx_EC(esr) == ESR_ELx_EC_BRK64 &&
|
||||
(esr_brk_comment(esr) & ~CFI_BRK_IMM_MASK) == CFI_BRK_IMM_BASE;
|
||||
}
|
||||
|
||||
static inline bool esr_fsc_is_translation_fault(unsigned long esr)
|
||||
{
|
||||
esr = esr & ESR_ELx_FSC;
|
||||
|
||||
return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
|
||||
(esr == ESR_ELx_FSC_FAULT_L(2)) ||
|
||||
(esr == ESR_ELx_FSC_FAULT_L(1)) ||
|
||||
(esr == ESR_ELx_FSC_FAULT_L(0)) ||
|
||||
(esr == ESR_ELx_FSC_FAULT_L(-1));
|
||||
}
|
||||
|
||||
static inline bool esr_fsc_is_permission_fault(unsigned long esr)
|
||||
{
|
||||
esr = esr & ESR_ELx_FSC;
|
||||
|
||||
return (esr == ESR_ELx_FSC_PERM_L(3)) ||
|
||||
(esr == ESR_ELx_FSC_PERM_L(2)) ||
|
||||
(esr == ESR_ELx_FSC_PERM_L(1)) ||
|
||||
(esr == ESR_ELx_FSC_PERM_L(0));
|
||||
}
|
||||
|
||||
static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
|
||||
{
|
||||
esr = esr & ESR_ELx_FSC;
|
||||
|
||||
return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
|
||||
(esr == ESR_ELx_FSC_ACCESS_L(2)) ||
|
||||
(esr == ESR_ELx_FSC_ACCESS_L(1)) ||
|
||||
(esr == ESR_ELx_FSC_ACCESS_L(0));
|
||||
}
|
||||
|
||||
/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */
|
||||
static inline bool esr_iss_is_eretax(unsigned long esr)
|
||||
{
|
||||
return esr & ESR_ELx_ERET_ISS_ERET;
|
||||
}
|
||||
|
||||
/* Indicate which key is used for ERETAx (false: A-Key, true: B-Key) */
|
||||
static inline bool esr_iss_is_eretab(unsigned long esr)
|
||||
{
|
||||
return esr & ESR_ELx_ERET_ISS_ERETA;
|
||||
}
|
||||
|
||||
const char *esr_get_class_string(unsigned long esr);
|
||||
#endif /* __ASSEMBLY */
|
||||
|
||||
#endif /* __ASM_ESR_H */
|
||||
|
|
@ -156,6 +156,7 @@ TEST_GEN_PROGS_aarch64 += aarch64/aarch32_id_regs
|
|||
TEST_GEN_PROGS_aarch64 += aarch64/arch_timer_edge_cases
|
||||
TEST_GEN_PROGS_aarch64 += aarch64/debug-exceptions
|
||||
TEST_GEN_PROGS_aarch64 += aarch64/hypercalls
|
||||
TEST_GEN_PROGS_aarch64 += aarch64/mmio_abort
|
||||
TEST_GEN_PROGS_aarch64 += aarch64/page_fault_test
|
||||
TEST_GEN_PROGS_aarch64 += aarch64/psci_test
|
||||
TEST_GEN_PROGS_aarch64 += aarch64/set_id_regs
|
||||
|
|
|
|||
|
|
@ -433,15 +433,15 @@ static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bp
|
|||
vcpu_init_descriptor_tables(vcpu);
|
||||
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_BRK_INS, guest_sw_bp_handler);
|
||||
ESR_ELx_EC_BRK64, guest_sw_bp_handler);
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_HW_BP_CURRENT, guest_hw_bp_handler);
|
||||
ESR_ELx_EC_BREAKPT_CUR, guest_hw_bp_handler);
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_WP_CURRENT, guest_wp_handler);
|
||||
ESR_ELx_EC_WATCHPT_CUR, guest_wp_handler);
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_SSTEP_CURRENT, guest_ss_handler);
|
||||
ESR_ELx_EC_SOFTSTP_CUR, guest_ss_handler);
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_SVC64, guest_svc_handler);
|
||||
ESR_ELx_EC_SVC64, guest_svc_handler);
|
||||
|
||||
/* Specify bpn/wpn/ctx_bpn to be tested */
|
||||
vcpu_args_set(vcpu, 3, bpn, wpn, ctx_bpn);
|
||||
|
|
|
|||
159
tools/testing/selftests/kvm/aarch64/mmio_abort.c
Normal file
159
tools/testing/selftests/kvm/aarch64/mmio_abort.c
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* mmio_abort - Tests for userspace MMIO abort injection
|
||||
*
|
||||
* Copyright (c) 2024 Google LLC
|
||||
*/
|
||||
#include "processor.h"
|
||||
#include "test_util.h"
|
||||
|
||||
#define MMIO_ADDR 0x8000000ULL
|
||||
|
||||
static u64 expected_abort_pc;
|
||||
|
||||
static void expect_sea_handler(struct ex_regs *regs)
|
||||
{
|
||||
u64 esr = read_sysreg(esr_el1);
|
||||
|
||||
GUEST_ASSERT_EQ(regs->pc, expected_abort_pc);
|
||||
GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_DABT_CUR);
|
||||
GUEST_ASSERT_EQ(esr & ESR_ELx_FSC_TYPE, ESR_ELx_FSC_EXTABT);
|
||||
|
||||
GUEST_DONE();
|
||||
}
|
||||
|
||||
static void unexpected_dabt_handler(struct ex_regs *regs)
|
||||
{
|
||||
GUEST_FAIL("Unexpected data abort at PC: %lx\n", regs->pc);
|
||||
}
|
||||
|
||||
static struct kvm_vm *vm_create_with_dabt_handler(struct kvm_vcpu **vcpu, void *guest_code,
|
||||
handler_fn dabt_handler)
|
||||
{
|
||||
struct kvm_vm *vm = vm_create_with_one_vcpu(vcpu, guest_code);
|
||||
|
||||
vm_init_descriptor_tables(vm);
|
||||
vcpu_init_descriptor_tables(*vcpu);
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT, ESR_ELx_EC_DABT_CUR, dabt_handler);
|
||||
|
||||
virt_map(vm, MMIO_ADDR, MMIO_ADDR, 1);
|
||||
|
||||
return vm;
|
||||
}
|
||||
|
||||
static void vcpu_inject_extabt(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct kvm_vcpu_events events = {};
|
||||
|
||||
events.exception.ext_dabt_pending = true;
|
||||
vcpu_events_set(vcpu, &events);
|
||||
}
|
||||
|
||||
static void vcpu_run_expect_done(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct ucall uc;
|
||||
|
||||
vcpu_run(vcpu);
|
||||
switch (get_ucall(vcpu, &uc)) {
|
||||
case UCALL_ABORT:
|
||||
REPORT_GUEST_ASSERT(uc);
|
||||
break;
|
||||
case UCALL_DONE:
|
||||
break;
|
||||
default:
|
||||
TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
|
||||
}
|
||||
}
|
||||
|
||||
extern char test_mmio_abort_insn;
|
||||
|
||||
static void test_mmio_abort_guest(void)
|
||||
{
|
||||
WRITE_ONCE(expected_abort_pc, (u64)&test_mmio_abort_insn);
|
||||
|
||||
asm volatile("test_mmio_abort_insn:\n\t"
|
||||
"ldr x0, [%0]\n\t"
|
||||
: : "r" (MMIO_ADDR) : "x0", "memory");
|
||||
|
||||
GUEST_FAIL("MMIO instruction should not retire");
|
||||
}
|
||||
|
||||
/*
|
||||
* Test that KVM doesn't complete MMIO emulation when userspace has made an
|
||||
* external abort pending for the instruction.
|
||||
*/
|
||||
static void test_mmio_abort(void)
|
||||
{
|
||||
struct kvm_vcpu *vcpu;
|
||||
struct kvm_vm *vm = vm_create_with_dabt_handler(&vcpu, test_mmio_abort_guest,
|
||||
expect_sea_handler);
|
||||
struct kvm_run *run = vcpu->run;
|
||||
|
||||
vcpu_run(vcpu);
|
||||
TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_MMIO);
|
||||
TEST_ASSERT_EQ(run->mmio.phys_addr, MMIO_ADDR);
|
||||
TEST_ASSERT_EQ(run->mmio.len, sizeof(unsigned long));
|
||||
TEST_ASSERT(!run->mmio.is_write, "Expected MMIO read");
|
||||
|
||||
vcpu_inject_extabt(vcpu);
|
||||
vcpu_run_expect_done(vcpu);
|
||||
kvm_vm_free(vm);
|
||||
}
|
||||
|
||||
extern char test_mmio_nisv_insn;
|
||||
|
||||
static void test_mmio_nisv_guest(void)
|
||||
{
|
||||
WRITE_ONCE(expected_abort_pc, (u64)&test_mmio_nisv_insn);
|
||||
|
||||
asm volatile("test_mmio_nisv_insn:\n\t"
|
||||
"ldr x0, [%0], #8\n\t"
|
||||
: : "r" (MMIO_ADDR) : "x0", "memory");
|
||||
|
||||
GUEST_FAIL("MMIO instruction should not retire");
|
||||
}
|
||||
|
||||
/*
|
||||
* Test that the KVM_RUN ioctl fails for ESR_EL2.ISV=0 MMIO aborts if userspace
|
||||
* hasn't enabled KVM_CAP_ARM_NISV_TO_USER.
|
||||
*/
|
||||
static void test_mmio_nisv(void)
|
||||
{
|
||||
struct kvm_vcpu *vcpu;
|
||||
struct kvm_vm *vm = vm_create_with_dabt_handler(&vcpu, test_mmio_nisv_guest,
|
||||
unexpected_dabt_handler);
|
||||
|
||||
TEST_ASSERT(_vcpu_run(vcpu), "Expected nonzero return code from KVM_RUN");
|
||||
TEST_ASSERT_EQ(errno, ENOSYS);
|
||||
|
||||
kvm_vm_free(vm);
|
||||
}
|
||||
|
||||
/*
|
||||
* Test that ESR_EL2.ISV=0 MMIO aborts reach userspace and that an injected SEA
|
||||
* reaches the guest.
|
||||
*/
|
||||
static void test_mmio_nisv_abort(void)
|
||||
{
|
||||
struct kvm_vcpu *vcpu;
|
||||
struct kvm_vm *vm = vm_create_with_dabt_handler(&vcpu, test_mmio_nisv_guest,
|
||||
expect_sea_handler);
|
||||
struct kvm_run *run = vcpu->run;
|
||||
|
||||
vm_enable_cap(vm, KVM_CAP_ARM_NISV_TO_USER, 1);
|
||||
|
||||
vcpu_run(vcpu);
|
||||
TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_ARM_NISV);
|
||||
TEST_ASSERT_EQ(run->arm_nisv.fault_ipa, MMIO_ADDR);
|
||||
|
||||
vcpu_inject_extabt(vcpu);
|
||||
vcpu_run_expect_done(vcpu);
|
||||
kvm_vm_free(vm);
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
test_mmio_abort();
|
||||
test_mmio_nisv();
|
||||
test_mmio_nisv_abort();
|
||||
}
|
||||
|
|
@ -150,7 +150,7 @@ static void test_guest_no_gicv3(void)
|
|||
vcpu_init_descriptor_tables(vcpu);
|
||||
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_UNKNOWN, guest_undef_handler);
|
||||
ESR_ELx_EC_UNKNOWN, guest_undef_handler);
|
||||
|
||||
test_run_vcpu(vcpu);
|
||||
|
||||
|
|
|
|||
|
|
@ -544,9 +544,9 @@ static void setup_abort_handlers(struct kvm_vm *vm, struct kvm_vcpu *vcpu,
|
|||
vcpu_init_descriptor_tables(vcpu);
|
||||
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_DABT, no_dabt_handler);
|
||||
ESR_ELx_EC_DABT_CUR, no_dabt_handler);
|
||||
vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,
|
||||
ESR_EC_IABT, no_iabt_handler);
|
||||
ESR_ELx_EC_IABT_CUR, no_iabt_handler);
|
||||
}
|
||||
|
||||
static void setup_gva_maps(struct kvm_vm *vm)
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ static void guest_sync_handler(struct ex_regs *regs)
|
|||
uint64_t esr, ec;
|
||||
|
||||
esr = read_sysreg(esr_el1);
|
||||
ec = (esr >> ESR_EC_SHIFT) & ESR_EC_MASK;
|
||||
ec = ESR_ELx_EC(esr);
|
||||
|
||||
__GUEST_ASSERT(expected_ec == ec,
|
||||
"PC: 0x%lx; ESR: 0x%lx; EC: 0x%lx; EC expected: 0x%lx",
|
||||
|
|
@ -338,10 +338,10 @@ static void test_access_invalid_pmc_regs(struct pmc_accessor *acc, int pmc_idx)
|
|||
* Reading/writing the event count/type registers should cause
|
||||
* an UNDEFINED exception.
|
||||
*/
|
||||
TEST_EXCEPTION(ESR_EC_UNKNOWN, acc->read_cntr(pmc_idx));
|
||||
TEST_EXCEPTION(ESR_EC_UNKNOWN, acc->write_cntr(pmc_idx, 0));
|
||||
TEST_EXCEPTION(ESR_EC_UNKNOWN, acc->read_typer(pmc_idx));
|
||||
TEST_EXCEPTION(ESR_EC_UNKNOWN, acc->write_typer(pmc_idx, 0));
|
||||
TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->read_cntr(pmc_idx));
|
||||
TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->write_cntr(pmc_idx, 0));
|
||||
TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->read_typer(pmc_idx));
|
||||
TEST_EXCEPTION(ESR_ELx_EC_UNKNOWN, acc->write_typer(pmc_idx, 0));
|
||||
/*
|
||||
* The bit corresponding to the (unimplemented) counter in
|
||||
* {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers should be RAZ.
|
||||
|
|
@ -425,7 +425,7 @@ static void create_vpmu_vm(void *guest_code)
|
|||
|
||||
vpmu_vm.vm = vm_create(1);
|
||||
vm_init_descriptor_tables(vpmu_vm.vm);
|
||||
for (ec = 0; ec < ESR_EC_NUM; ec++) {
|
||||
for (ec = 0; ec < ESR_ELx_EC_MAX + 1; ec++) {
|
||||
vm_install_sync_handler(vpmu_vm.vm, VECTOR_SYNC_CURRENT, ec,
|
||||
guest_sync_handler);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
#include <linux/stringify.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/brk-imm.h>
|
||||
#include <asm/esr.h>
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
|
||||
|
|
@ -100,19 +102,6 @@ enum {
|
|||
(v) == VECTOR_SYNC_LOWER_64 || \
|
||||
(v) == VECTOR_SYNC_LOWER_32)
|
||||
|
||||
#define ESR_EC_NUM 64
|
||||
#define ESR_EC_SHIFT 26
|
||||
#define ESR_EC_MASK (ESR_EC_NUM - 1)
|
||||
|
||||
#define ESR_EC_UNKNOWN 0x0
|
||||
#define ESR_EC_SVC64 0x15
|
||||
#define ESR_EC_IABT 0x21
|
||||
#define ESR_EC_DABT 0x25
|
||||
#define ESR_EC_HW_BP_CURRENT 0x31
|
||||
#define ESR_EC_SSTEP_CURRENT 0x33
|
||||
#define ESR_EC_WP_CURRENT 0x35
|
||||
#define ESR_EC_BRK_INS 0x3c
|
||||
|
||||
/* Access flag */
|
||||
#define PTE_AF (1ULL << 10)
|
||||
|
||||
|
|
|
|||
|
|
@ -450,7 +450,7 @@ void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
|
|||
}
|
||||
|
||||
struct handlers {
|
||||
handler_fn exception_handlers[VECTOR_NUM][ESR_EC_NUM];
|
||||
handler_fn exception_handlers[VECTOR_NUM][ESR_ELx_EC_MAX + 1];
|
||||
};
|
||||
|
||||
void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu)
|
||||
|
|
@ -469,7 +469,7 @@ void route_exception(struct ex_regs *regs, int vector)
|
|||
switch (vector) {
|
||||
case VECTOR_SYNC_CURRENT:
|
||||
case VECTOR_SYNC_LOWER_64:
|
||||
ec = (read_sysreg(esr_el1) >> ESR_EC_SHIFT) & ESR_EC_MASK;
|
||||
ec = ESR_ELx_EC(read_sysreg(esr_el1));
|
||||
valid_ec = true;
|
||||
break;
|
||||
case VECTOR_IRQ_CURRENT:
|
||||
|
|
@ -508,7 +508,7 @@ void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec,
|
|||
|
||||
assert(VECTOR_IS_SYNC(vector));
|
||||
assert(vector < VECTOR_NUM);
|
||||
assert(ec < ESR_EC_NUM);
|
||||
assert(ec <= ESR_ELx_EC_MAX);
|
||||
handlers->exception_handlers[vector][ec] = handler;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user