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mmc: rk_sdmmc: add platform hook for special pm ops during deepsleep
We register a platform hook and restore all of our regs if platform does need to cutoff controller's power-supply during deepsleep in period of time. Make sure your have added "controller-power-down" property AND comment out "keep-power-in-suspend" in related dts file. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Xiaoyao <xiaoyao@rock-chips.com> Reviewed-by: Chenjh <chenjh@rock-chips.com> Tested-by: Chenjh <chenjh@rock-chips.com>
This commit is contained in:
lintao
Shawn Lin
parent
db270573b2
commit
4bb5de4aae
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@ -79,6 +79,9 @@
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#define SDMMC_CMD_RTO_MAX_HOLD 200
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#define SDMMC_WAIT_FOR_UNBUSY 2500
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#define DW_REGS_SIZE (0x0098 + 4)
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#define DW_REGS_NUM (0x0098 / 4)
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#ifdef CONFIG_MMC_DW_IDMAC
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#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
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SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
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@ -3778,6 +3781,43 @@ static inline bool dw_mci_ctrl_all_reset(struct dw_mci *host)
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SDMMC_CTRL_DMA_RESET);
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}
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static void dw_mci_rst_pre_suspend(struct dw_mci *host)
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{
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u32 index;
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u32 *buffer;
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buffer = host->regs_buffer;
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for (index = 0; index < DW_REGS_NUM ; index++){
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*buffer = mci_readreg(host, index*4);
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MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n",
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dw_mci_regs[index].name, *buffer);
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buffer++;
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}
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*buffer = mci_readl(host,CDTHRCTL);
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MMC_DBG_INFO_FUNC(host->mmc, "[%s] :0x%08x.\n", "CARDTHRCTL", *buffer);
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}
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static void dw_mci_rst_post_resume(struct dw_mci *host)
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{
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u32 index;
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u32 *buffer;
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buffer = host->regs_buffer;
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for (index = 0; index < DW_REGS_NUM; index++){
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mci_writereg(host, index*4, *buffer);
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buffer++;
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}
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mci_writel(host, CDTHRCTL, *buffer);
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}
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static const struct dw_mci_rst_ops dw_mci_pdrst_ops = {
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.pre_suspend = dw_mci_rst_pre_suspend,
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.post_resume = dw_mci_rst_post_resume,
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};
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#ifdef CONFIG_OF
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/*
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static struct dw_mci_of_quirks {
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@ -3861,7 +3901,20 @@ static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
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if (of_get_property(np, "cd-inverted", NULL))
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pdata->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
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if (of_get_property(np, "bootpart-no-access", NULL))
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pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
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pdata->caps2 |= MMC_CAP2_BOOTPART_NOACC;
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if (of_get_property(np, "controller-power-down", NULL)) {
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host->regs_buffer = (u32 *)devm_kzalloc(host->dev,
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DW_REGS_SIZE, GFP_KERNEL);
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if (!host->regs_buffer) {
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dev_err(host->dev,
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"could not allocate memory for regs_buffer\n");
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return ERR_PTR(-ENOMEM);
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}
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host->rst_ops = &dw_mci_pdrst_ops;
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mmc_assume_removable = 0;
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}
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return pdata;
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}
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@ -4200,6 +4253,11 @@ int dw_mci_suspend(struct dw_mci *host)
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enable_irq_wake(host->mmc->slot.cd_irq);
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}
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}
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if (host->rst_ops &&
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host->rst_ops->pre_suspend)
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host->rst_ops->pre_suspend(host);
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return 0;
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}
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EXPORT_SYMBOL(dw_mci_suspend);
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@ -4211,6 +4269,11 @@ int dw_mci_resume(struct dw_mci *host)
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struct dw_mci_slot *slot;
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int present = dw_mci_get_cd(host->mmc);
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if (host->rst_ops &&
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host->rst_ops->post_resume)
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host->rst_ops->post_resume(host);
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if ((host->mmc->restrict_caps & RESTRICT_CARD_TYPE_SDIO) &&
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(get_wifi_chip_type() == WIFI_ESP8089 ||
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get_wifi_chip_type() > WIFI_AP6XXX_SERIES))
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@ -77,52 +77,50 @@ u32 addr;
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char *name;
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};
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#if 0
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static struct sdmmc_reg dw_mci_regs[] =
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{
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{ 0x0000, " CTRL" },
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{ 0x0004, " PWREN" },
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{ 0x0008, " CLKDIV" },
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{ 0x000C, " CLKSRC" },
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{ 0x0010, " CLKENA" },
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{ 0x0014, " TMOUT" },
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{ 0x0018, " CTYPE" },
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{ 0x001C, " BLKSIZ" },
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{ 0x0020, " BYTCNT" },
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{ 0x0024, " INTMASK" },
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{ 0x0028, " CMDARG" },
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{ 0x002C, " CMD" },
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{ 0x0030, " RESP0" },
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{ 0x0034, " RESP1" },
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{ 0x0038, " RESP2" },
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{ 0x003C, " RESP3" },
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{ 0x0040, " MINSTS" },
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{ 0x0044, " RINTSTS" },
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{ 0x0048, " STATUS" },
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{ 0x004C, " FIFOTH" },
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{ 0x0050, " CDETECT" },
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{ 0x0054, " WRTPRT" },
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{ 0x0058, " GPIO" },
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{ 0x005C, " TCBCNT" },
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{ 0x0060, " TBBCNT" },
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{ 0x0064, " DEBNCE" },
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{ 0x0068, " USRID" },
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{ 0x006C, " VERID" },
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{ 0x0070, " HCON" },
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{ 0x0074, " UHS_REG" },
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{ 0x0078, " RST_n" },
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{ 0x0080, " BMOD" },
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{ 0x0084, " PLDMND" },
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{ 0x0088, " DBADDR" },
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{ 0x008C, " IDSTS" },
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{ 0x0090, " IDINTEN" },
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{ 0x0094, " DSCADDR" },
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{ 0x0098, " BUFADDR" },
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{ 0x0000, "CTRL" },
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{ 0x0004, "PWREN" },
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{ 0x0008, "CLKDIV" },
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{ 0x000C, "CLKSRC" },
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{ 0x0010, "CLKENA" },
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{ 0x0014, "TMOUT" },
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{ 0x0018, "CTYPE" },
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{ 0x001C, "BLKSIZ" },
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{ 0x0020, "BYTCNT" },
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{ 0x0024, "INTMASK" },
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{ 0x0028, "CMDARG" },
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{ 0x002C, "CMD" },
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{ 0x0030, "RESP0" },
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{ 0x0034, "RESP1" },
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{ 0x0038, "RESP2" },
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{ 0x003C, "RESP3" },
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{ 0x0040, "MINSTS" },
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{ 0x0044, "RINTSTS" },
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{ 0x0048, "STATUS" },
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{ 0x004C, "FIFOTH" },
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{ 0x0050, "CDETECT" },
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{ 0x0054, "WRTPRT" },
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{ 0x0058, "GPIO" },
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{ 0x005C, "TCBCNT" },
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{ 0x0060, "TBBCNT" },
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{ 0x0064, "DEBNCE" },
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{ 0x0068, "USRID" },
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{ 0x006C, "VERID" },
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{ 0x0070, "HCON" },
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{ 0x0074, "UHS_REG" },
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{ 0x0078, "RST_n" },
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{ 0x0080, "BMOD" },
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{ 0x0084, "PLDMND" },
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{ 0x0088, "DBADDR" },
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{ 0x008C, "IDSTS" },
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{ 0x0090, "IDINTEN" },
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{ 0x0094, "DSCADDR" },
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{ 0x0098, "BUFADDR" },
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{ 0x0100, "CARDTHRCTL" },
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{ 0x0104, "BackEndPwr" },
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{ 0, 0 }
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};
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#endif
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/* Control register defines */
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#define SDMMC_CTRL_USE_IDMAC BIT(25)
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@ -233,6 +231,9 @@ static struct sdmmc_reg dw_mci_regs[] =
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__raw_writel((value), (dev)->regs + SDMMC_##reg)
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#define mci_readreg(dev, addr) \
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__raw_readl((dev)->regs + addr)
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#define mci_writereg(dev, addr, value) \
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__raw_writel((value), (dev)->regs + addr)
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/* 16-bit FIFO access macros */
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#define mci_readw(dev, reg) \
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@ -218,6 +218,8 @@ struct dw_mci {
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u32 cid;
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struct regmap *grf;
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u32 *regs_buffer;
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const struct dw_mci_rst_ops *rst_ops;
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};
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/* DMA ops for Internal/External DMAC interface */
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@ -231,6 +233,12 @@ struct dw_mci_dma_ops {
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void (*exit)(struct dw_mci *host);
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};
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/* Platform rst hook for pm ops before suspend and after resume */
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struct dw_mci_rst_ops {
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void (*pre_suspend)(struct dw_mci *host);
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void (*post_resume)(struct dw_mci *host);
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};
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/* IP Quirks/flags. */
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/* DTO fix for command transmission with IDMAC configured */
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#define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
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