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drm/i915/gen9_bc: Recognize TGP PCH + CML combos
Since Intel has introduced the gen9_bc platform, a combination of Tigerpoint PCHs and CML CPUs, let's recognize such platforms as valid and avoid WARNing on them. Changes since v4: * Split this into it's own patch - vsyrjala Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> [originally from Tejas's work] Signed-off-by: Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210209212832.1401815-2-lyude@redhat.com
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@ -121,7 +121,8 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
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case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
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drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
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drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
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!IS_ROCKETLAKE(dev_priv));
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!IS_ROCKETLAKE(dev_priv) &&
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!IS_GEN9_BC(dev_priv));
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return PCH_TGP;
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case INTEL_PCH_JSP_DEVICE_ID_TYPE:
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case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
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