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drm/amd/display: fix mpo blanking out on one of planes being set not visible

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Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2017-05-11 17:15:14 -04:00 committed by Alex Deucher
parent 747be97f4e
commit 4b28b76bfe
7 changed files with 51 additions and 37 deletions
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3
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
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@ -403,8 +403,7 @@ void dce_mem_input_program_surface_config(struct mem_input *mi,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
bool visible)
bool horizontal_mirror)
{
REG_UPDATE(GRPH_ENABLE, GRPH_ENABLE, 1);

3
drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h
View File

@ -277,8 +277,7 @@ void dce_mem_input_program_surface_config(struct mem_input *mi,
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
bool visible);
bool horizontal_mirror);
void dce_mem_input_allocate_dmif(struct mem_input *mi,
uint32_t h_total,

10
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1986,8 +1986,9 @@ static void set_plane_config(
&surface->public.plane_size,
surface->public.rotation,
NULL,
false,
pipe_ctx->surface->public.visible);
false);
if (mi->funcs->set_blank)
mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
@ -2432,8 +2433,9 @@ static void dce110_program_front_end_for_pipe(
&surface->public.plane_size,
surface->public.rotation,
NULL,
false,
pipe_ctx->surface->public.visible);
false);
if (mi->funcs->set_blank)
mi->funcs->set_blank(mi, pipe_ctx->surface->public.visible);
if (dc->public.config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(

3
drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input_v.c
View File

@ -664,8 +664,7 @@ void dce110_mem_input_v_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizotal_mirror,
bool visible)
bool horizotal_mirror)
{
struct dce110_mem_input *mem_input110 = TO_DCE110_MEM_INPUT(mem_input);

41
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
View File

@ -848,7 +848,7 @@ static void reset_front_end_for_pipe(
unlock_master_tg_and_wait(dc->ctx, pipe_ctx->tg->inst);
pipe_ctx->mi->funcs->disable_request(pipe_ctx->mi);
pipe_ctx->mi->funcs->set_blank(pipe_ctx->mi, true);
wait_no_outstanding_request(dc->ctx, pipe_ctx->pipe_idx);
@ -1513,6 +1513,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
}
static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->surface->public.visible)
return true;
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
return true;
return false;
}
static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->surface->public.visible)
return true;
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
return true;
return false;
}
static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
{
if (pipe_ctx->surface->public.visible)
return true;
if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
return true;
if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
return true;
return false;
}
static void update_dchubp_dpp(
struct core_dc *dc,
struct pipe_ctx *pipe_ctx,
@ -1633,12 +1662,9 @@ static void update_dchubp_dpp(
&size,
surface->public.rotation,
&surface->public.dcc,
surface->public.horizontal_mirror,
surface->public.visible);
/* Only support one plane for now. */
pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !surface->public.visible);
surface->public.horizontal_mirror);
mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx));
}
static void program_all_pipe_in_tree(
@ -1669,10 +1695,13 @@ static void program_all_pipe_in_tree(
pipe_ctx->tg->funcs->program_global_sync(
pipe_ctx->tg);
pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx));
update_dchubp_dpp(dc, pipe_ctx, context);
/* Only support one plane for now. */
}
if (pipe_ctx->bottom_pipe != NULL)

20
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
View File

@ -38,8 +38,9 @@
#define FN(reg_name, field_name) \
mi->mi_shift->field_name, mi->mi_mask->field_name
static void set_blank(struct dcn10_mem_input *mi, bool blank)
static void dcn_mi_set_blank(struct mem_input *mem_input, bool blank)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
uint32_t blank_en = blank ? 1 : 0;
REG_UPDATE_2(DCHUBP_CNTL,
@ -47,15 +48,6 @@ static void set_blank(struct dcn10_mem_input *mi, bool blank)
HUBP_TTU_DISABLE, blank_en);
}
static void disable_request(struct mem_input *mem_input)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
/* To disable the requestors, set blank_en to 1 */
set_blank(mi, true);
}
static void vready_workaround(struct mem_input *mem_input,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
{
@ -402,8 +394,7 @@ static void mem_input_program_surface_config(
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
bool visible)
bool horizontal_mirror)
{
struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
@ -412,8 +403,6 @@ static void mem_input_program_surface_config(
program_size_and_rotation(
mi, rotation, format, plane_size, dcc, horizontal_mirror);
program_pixel_format(mi, format);
set_blank(mi, !visible);
}
static void program_requestor(
@ -573,7 +562,6 @@ static void mem_input_setup(
/* otg is locked when this func is called. Register are double buffered.
* disable the requestors is not needed
*/
/* disable_request(mem_input); */
program_requestor(mem_input, rq_regs);
program_deadline(mem_input, dlg_attr, ttu_attr);
vready_workaround(mem_input, pipe_dest);
@ -1065,7 +1053,6 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
.mem_input_program_display_marks = mem_input_program_display_marks,
.allocate_mem_input = NULL,
.free_mem_input = NULL,
.disable_request = disable_request,
.mem_input_program_surface_flip_and_addr =
mem_input_program_surface_flip_and_addr,
.mem_input_program_surface_config =
@ -1075,6 +1062,7 @@ static struct mem_input_funcs dcn10_mem_input_funcs = {
.program_watermarks = program_watermarks,
.mem_input_update_dchub = mem_input_update_dchub,
.mem_input_program_pte_vm = dcn_mem_input_program_pte_vm,
.set_blank = dcn_mi_set_blank,
};

8
drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
View File

@ -94,9 +94,6 @@ struct mem_input_funcs {
struct _vcs_dpi_display_ttu_regs_st *ttu_regs,
struct _vcs_dpi_display_rq_regs_st *rq_regs,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
void (*disable_request)(struct mem_input *mem_input);
#endif
void (*mem_input_program_display_marks)(
@ -142,13 +139,14 @@ struct mem_input_funcs {
union plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
bool horizontal_mirror,
bool visible);
bool horizontal_mirror);
bool (*mem_input_is_flip_pending)(struct mem_input *mem_input);
void (*mem_input_update_dchub)(struct mem_input *mem_input,
struct dchub_init_data *dh_data);
void (*set_blank)(struct mem_input *mi, bool blank);
};
#endif