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ARM: dts: sti: move usb picophy nodes out of soc in stih410.dtsi

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Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
Since they are controlled via syscfg, there is no reg property needed,
which is required when having the node within the soc section.

Modification is done within stih410.dtsi and within related board
dts files (stih410-b2120.dts, stih410-b2260.dts).

Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Alain Volmat 2022-02-11 19:16:13 +01:00 committed by Patrice Chotard
parent a7436e34e9
commit 4b151244ff
3 changed files with 38 additions and 40 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/boot/dts/stih410-b2120.dts
View File

@ -24,6 +24,14 @@ aliases {
ethernet0 = &ethernet0;
};
usb2_picophy1: phy2 {
status = "okay";
};
usb2_picophy2: phy3 {
status = "okay";
};
soc {
mmc0: sdhci@9060000 {
@ -33,14 +41,6 @@ mmc0: sdhci@9060000 {
sd-uhs-ddr50;
};
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3@0 {
status = "okay";
};
ohci0: usb@9a03c00 {
status = "okay";
};

16
arch/arm/boot/dts/stih410-b2260.dts
View File

@ -82,6 +82,14 @@ phy_port1: port@9b2a000 {
};
};
usb2_picophy1: phy2 {
status = "okay";
};
usb2_picophy2: phy3 {
status = "okay";
};
soc {
/* Low speed expansion connector */
uart0: serial@9830000 {
@ -152,14 +160,6 @@ pwm1: pwm@9510000 {
status = "okay";
};
usb2_picophy1: phy2@0 {
status = "okay";
};
usb2_picophy2: phy3@0 {
status = "okay";
};
ohci0: usb@9a03c00 {
status = "okay";
};

46
arch/arm/boot/dts/stih410.dtsi
View File

@ -12,31 +12,29 @@ aliases {
bdisp0 = &bdisp0;
};
usb2_picophy1: phy2 {
compatible = "st,stih407-usb2-phy";
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY0_RESET>;
reset-names = "global", "port";
status = "disabled";
};
usb2_picophy2: phy3 {
compatible = "st,stih407-usb2-phy";
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY1_RESET>;
reset-names = "global", "port";
status = "disabled";
};
soc {
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xf8 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY0_RESET>;
reset-names = "global", "port";
status = "disabled";
};
usb2_picophy2: phy3@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
#phy-cells = <0>;
st,syscfg = <&syscfg_core 0xfc 0xf4>;
resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
<&picophyreset STIH407_PICOPHY1_RESET>;
reset-names = "global", "port";
status = "disabled";
};
ohci0: usb@9a03c00 {
compatible = "st,st-ohci-300x";
reg = <0x9a03c00 0x100>;