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arm64: dts: mt8192: Add m4u and smi nodes

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Add m4u and smi nodes for mt8192 SoC

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20220318144534.17996-15-allen-kh.cheng@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Allen-KH Cheng 2022-03-18 22:45:26 +08:00 committed by Matthias Brugger
parent 4d50a433d0
commit 4a65b0f1be
1 changed files with 190 additions and 0 deletions
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190
arch/arm64/boot/dts/mediatek/mt8192.dtsi
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@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8192-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
@ -967,24 +968,114 @@ mmsys: syscon@14000000 {
#clock-cells = <1>;
};
smi_common: smi@14002000 {
compatible = "mediatek,mt8192-smi-common";
reg = <0 0x14002000 0 0x1000>;
clocks = <&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_GALS>;
clock-names = "apb", "smi", "gals0", "gals1";
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
larb0: larb@14003000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x14003000 0 0x1000>;
mediatek,larb-id = <0>;
mediatek,smi = <&smi_common>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
larb1: larb@14004000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x14004000 0 0x1000>;
mediatek,larb-id = <1>;
mediatek,smi = <&smi_common>;
clocks = <&clk26m>, <&clk26m>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
};
iommu0: m4u@1401d000 {
compatible = "mediatek,mt8192-m4u";
reg = <0 0x1401d000 0 0x1000>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
<&larb4>, <&larb5>, <&larb7>,
<&larb9>, <&larb11>, <&larb13>,
<&larb14>, <&larb16>, <&larb17>,
<&larb18>, <&larb19>, <&larb20>;
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "bclk";
power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
#iommu-cells = <1>;
};
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
larb9: larb@1502e000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1502e000 0 0x1000>;
mediatek,larb-id = <9>;
mediatek,smi = <&smi_common>;
clocks = <&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_LARB9>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
};
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
larb11: larb@1582e000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1582e000 0 0x1000>;
mediatek,larb-id = <11>;
mediatek,smi = <&smi_common>;
clocks = <&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_LARB11>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
mediatek,larb-id = <5>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
};
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
larb4: larb@1602e000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1602e000 0 0x1000>;
mediatek,larb-id = <4>;
mediatek,smi = <&smi_common>;
clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
<&vdecsys CLK_VDEC_SOC_LARB1>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
};
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
@ -997,12 +1088,78 @@ vencsys: clock-controller@17000000 {
#clock-cells = <1>;
};
larb7: larb@17010000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x17010000 0 0x1000>;
mediatek,larb-id = <7>;
mediatek,smi = <&smi_common>;
clocks = <&vencsys CLK_VENC_SET0_LARB>,
<&vencsys CLK_VENC_SET1_VENC>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
};
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
larb13: larb@1a001000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a001000 0 0x1000>;
mediatek,larb-id = <13>;
mediatek,smi = <&smi_common>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_LARB13>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
};
larb14: larb@1a002000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a002000 0 0x1000>;
mediatek,larb-id = <14>;
mediatek,smi = <&smi_common>;
clocks = <&camsys CLK_CAM_CAM>,
<&camsys CLK_CAM_LARB14>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
};
larb16: larb@1a00f000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a00f000 0 0x1000>;
mediatek,larb-id = <16>;
mediatek,smi = <&smi_common>;
clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
<&camsys_rawa CLK_CAM_RAWA_LARBX>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
};
larb17: larb@1a010000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a010000 0 0x1000>;
mediatek,larb-id = <17>;
mediatek,smi = <&smi_common>;
clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
<&camsys_rawb CLK_CAM_RAWB_LARBX>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
};
larb18: larb@1a011000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1a011000 0 0x1000>;
mediatek,larb-id = <18>;
mediatek,smi = <&smi_common>;
clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
<&camsys_rawc CLK_CAM_RAWC_CAM>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
};
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
@ -1027,10 +1184,43 @@ ipesys: clock-controller@1b000000 {
#clock-cells = <1>;
};
larb20: larb@1b00f000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1b00f000 0 0x1000>;
mediatek,larb-id = <20>;
mediatek,smi = <&smi_common>;
clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_LARB20>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
};
larb19: larb@1b10f000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1b10f000 0 0x1000>;
mediatek,larb-id = <19>;
mediatek,smi = <&smi_common>;
clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_LARB19>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
};
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
larb2: larb@1f002000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1f002000 0 0x1000>;
mediatek,larb-id = <2>;
mediatek,smi = <&smi_common>;
clocks = <&mdpsys CLK_MDP_SMI0>,
<&mdpsys CLK_MDP_SMI0>;
clock-names = "apb", "smi";
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
};