From bd352547df647be8a1e6c9d4ca2b54b459f3abc1 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:29:59 -0500 Subject: [PATCH 1/7] spi: dt-bindings: fsl-qspi: support SpacemiT K1 Add the SpacemiT K1 SoC QSPI IP to the list of supported hardware. This is the first non-Freescale device represented here. It has a nearly identidal register set, and this binding correctly describes the hardware. Acked-by: Conor Dooley Reviewed-by: Frank Li Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-2-elder@riscstar.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml index f2dd20370dbb..5e6aff1bc2ed 100644 --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml @@ -22,6 +22,7 @@ properties: - fsl,imx6ul-qspi - fsl,ls1021a-qspi - fsl,ls2080a-qspi + - spacemit,k1-qspi - items: - enum: - fsl,ls1043a-qspi From 873a46141460d209bb62eaa0dc9e7b67bff924a6 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:00 -0500 Subject: [PATCH 2/7] spi: dt-bindings: fsl-qspi: add optional resets Allow two resets to be defined to support the SpacemiT K1 SoC QSPI IP. Move the allOf block down, below the required section. Reviewed-by: Frank Li Acked-by: Conor Dooley Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-3-elder@riscstar.com Signed-off-by: Mark Brown --- .../bindings/spi/fsl,spi-fsl-qspi.yaml | 20 ++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml index 5e6aff1bc2ed..1d10cfbad86c 100644 --- a/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml @@ -9,9 +9,6 @@ title: Freescale Quad Serial Peripheral Interface (QuadSPI) maintainers: - Han Xu -allOf: - - $ref: spi-controller.yaml# - properties: compatible: oneOf: @@ -55,6 +52,11 @@ properties: - const: qspi_en - const: qspi + resets: + items: + - description: SoC QSPI reset + - description: SoC QSPI bus reset + required: - compatible - reg @@ -63,6 +65,18 @@ required: - clocks - clock-names +allOf: + - $ref: spi-controller.yaml# + - if: + properties: + compatible: + not: + contains: + const: spacemit,k1-qspi + then: + properties: + resets: false + unevaluatedProperties: false examples: From 106d7641e55a472e7523c1f525c77fb6d420064d Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:01 -0500 Subject: [PATCH 3/7] spi: fsl-qspi: add optional reset support Add support for one or more optional exclusive resets. These simply need to be deasserted at probe time, and can remain that way for the life of the device. Reviewed-by: Frank Li Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-4-elder@riscstar.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-qspi.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index c887abb028d7..1e27647dd2a0 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -36,6 +36,7 @@ #include #include #include +#include #include #include @@ -267,6 +268,7 @@ struct fsl_qspi { const struct fsl_qspi_devtype_data *devtype_data; struct mutex lock; struct completion c; + struct reset_control *resets; struct clk *clk, *clk_en; struct pm_qos_request pm_qos_req; struct device *dev; @@ -857,6 +859,8 @@ static void fsl_qspi_cleanup(void *data) { struct fsl_qspi *q = data; + reset_control_assert(q->resets); + fsl_qspi_clk_disable_unprep(q); mutex_destroy(&q->lock); @@ -902,6 +906,10 @@ static int fsl_qspi_probe(struct platform_device *pdev) if (!q->ahb_addr) return -ENOMEM; + q->resets = devm_reset_control_array_get_optional_exclusive(dev); + if (IS_ERR(q->resets)) + return PTR_ERR(q->resets); + /* find the clocks */ q->clk_en = devm_clk_get(dev, "qspi_en"); if (IS_ERR(q->clk_en)) @@ -923,6 +931,10 @@ static int fsl_qspi_probe(struct platform_device *pdev) if (ret) return ret; + ret = reset_control_deassert(q->resets); + if (ret) + return ret; + /* find the irq */ ret = platform_get_irq(pdev, 0); if (ret < 0) From 6b398c1d3da7a673b13b1857f9fff4c15ee20cef Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:02 -0500 Subject: [PATCH 4/7] spi: fsl-qspi: switch predicates to bool Change all the needs_*() functions so they are no longer inline, and return bool rather than int. Reviewed-by: Frank Li Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-5-elder@riscstar.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-qspi.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 1e27647dd2a0..1944e63169d3 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -276,34 +276,34 @@ struct fsl_qspi { u32 memmap_phy; }; -static inline int needs_swap_endian(struct fsl_qspi *q) +static bool needs_swap_endian(struct fsl_qspi *q) { - return q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN; + return !!(q->devtype_data->quirks & QUADSPI_QUIRK_SWAP_ENDIAN); } -static inline int needs_4x_clock(struct fsl_qspi *q) +static bool needs_4x_clock(struct fsl_qspi *q) { - return q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK; + return !!(q->devtype_data->quirks & QUADSPI_QUIRK_4X_INT_CLK); } -static inline int needs_fill_txfifo(struct fsl_qspi *q) +static bool needs_fill_txfifo(struct fsl_qspi *q) { - return q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890; + return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT253890); } -static inline int needs_wakeup_wait_mode(struct fsl_qspi *q) +static bool needs_wakeup_wait_mode(struct fsl_qspi *q) { - return q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618; + return !!(q->devtype_data->quirks & QUADSPI_QUIRK_TKT245618); } -static inline int needs_amba_base_offset(struct fsl_qspi *q) +static bool needs_amba_base_offset(struct fsl_qspi *q) { return !(q->devtype_data->quirks & QUADSPI_QUIRK_BASE_INTERNAL); } -static inline int needs_tdh_setting(struct fsl_qspi *q) +static bool needs_tdh_setting(struct fsl_qspi *q) { - return q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING; + return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING); } /* From 1797d254f5c4b46b295527a635af7321a3fe1318 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:03 -0500 Subject: [PATCH 5/7] spi: fsl-qspi: add a clock disable quirk The SpacemiT K1 SoC QSPI implementation needs to avoid shutting off the clock when changing its rate. Add a new quirk to indicate that disabling and enabling the clock should be skipped when changing its rate. Reviewed-by: Frank Li Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-6-elder@riscstar.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-qspi.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 1944e63169d3..2c030dd6facc 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -197,6 +197,11 @@ */ #define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5) +/* + * Do not disable the "qspi" clock when changing its rate. + */ +#define QUADSPI_QUIRK_SKIP_CLK_DISABLE BIT(6) + struct fsl_qspi_devtype_data { unsigned int rxfifo; unsigned int txfifo; @@ -306,6 +311,11 @@ static bool needs_tdh_setting(struct fsl_qspi *q) return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING); } +static bool needs_clk_disable(struct fsl_qspi *q) +{ + return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE); +} + /* * An IC bug makes it necessary to rearrange the 32-bit data. * Later chips, such as IMX6SLX, have fixed this bug. @@ -536,15 +546,18 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct spi_device *spi, if (needs_4x_clock(q)) rate *= 4; - fsl_qspi_clk_disable_unprep(q); + if (needs_clk_disable(q)) + fsl_qspi_clk_disable_unprep(q); ret = clk_set_rate(q->clk, rate); if (ret) return; - ret = fsl_qspi_clk_prep_enable(q); - if (ret) - return; + if (needs_clk_disable(q)) { + ret = fsl_qspi_clk_prep_enable(q); + if (ret) + return; + } q->selected = spi_get_chipselect(spi, 0); From 56931105074fe7e5fc9d54e3163df3b95075643c Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:04 -0500 Subject: [PATCH 6/7] spi: fsl-qspi: introduce sfa_size devtype data In fsl_qspi_default_setup(), four registers define the size of blocks of data to written to each of four chips that comprise SPI NOR flash storage. They are currently defined to be the same as the AHB buffer size. The SpacemiT QSPI has an AHB buffer size of 512 bytes, but requires these four sizes to be multiples of 1024 bytes. Define a new field sfa_size in the fsl_qspi_devtype_data structure that, if non-zero, will be used instead of the AHB buffer size to define the size of these chip regions. Reviewed-by: Frank Li Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-7-elder@riscstar.com Signed-off-by: Mark Brown --- drivers/spi/spi-fsl-qspi.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 2c030dd6facc..46a3187b3354 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -207,6 +207,7 @@ struct fsl_qspi_devtype_data { unsigned int txfifo; int invalid_mstrid; unsigned int ahb_buf_size; + unsigned int sfa_size; unsigned int quirks; bool little_endian; }; @@ -737,6 +738,7 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) { void __iomem *base = q->iobase; u32 reg, addr_offset = 0; + u32 sfa_size; int ret; /* disable and unprepare clock to avoid glitch pass to controller */ @@ -795,17 +797,17 @@ static int fsl_qspi_default_setup(struct fsl_qspi *q) * In HW there can be a maximum of four chips on two buses with * two chip selects on each bus. We use four chip selects in SW * to differentiate between the four chips. - * We use ahb_buf_size for each chip and set SFA1AD, SFA2AD, SFB1AD, - * SFB2AD accordingly. + * + * By default we write the AHB buffer size to each chip, but + * a different size can be specified with devtype_data->sfa_size. + * The SFA1AD, SFA2AD, SFB1AD, and SFB2AD registers define the + * top (end) of these four regions. */ - qspi_writel(q, q->devtype_data->ahb_buf_size + addr_offset, - base + QUADSPI_SFA1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 2 + addr_offset, - base + QUADSPI_SFA2AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 3 + addr_offset, - base + QUADSPI_SFB1AD); - qspi_writel(q, q->devtype_data->ahb_buf_size * 4 + addr_offset, - base + QUADSPI_SFB2AD); + sfa_size = q->devtype_data->sfa_size ? : q->devtype_data->ahb_buf_size; + qspi_writel(q, addr_offset + 1 * sfa_size, base + QUADSPI_SFA1AD); + qspi_writel(q, addr_offset + 2 * sfa_size, base + QUADSPI_SFA2AD); + qspi_writel(q, addr_offset + 3 * sfa_size, base + QUADSPI_SFB1AD); + qspi_writel(q, addr_offset + 4 * sfa_size, base + QUADSPI_SFB2AD); q->selected = -1; From abc9a349b87ac0fd3ba8787ca00971b59c2e1257 Mon Sep 17 00:00:00 2001 From: Alex Elder Date: Mon, 27 Oct 2025 08:30:05 -0500 Subject: [PATCH 7/7] spi: fsl-qspi: support the SpacemiT K1 SoC Allow the SPI_FSL_QUADSPI Kconfig option to be selected if ARCH_SPACEMIT enabled. Add support for the SpacemiT K1 SoC in the Freescale QSPI driver by defining the device type data for its QSPI implementation. Signed-off-by: Alex Elder Link: https://patch.msgid.link/20251027133008.360237-8-elder@riscstar.com Signed-off-by: Mark Brown --- drivers/spi/Kconfig | 3 ++- drivers/spi/spi-fsl-qspi.c | 11 +++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4d8f00c850c1..592d46c9998b 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -435,7 +435,8 @@ config SPI_FSL_LPSPI config SPI_FSL_QUADSPI tristate "Freescale QSPI controller" - depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || COMPILE_TEST + depends on ARCH_MXC || SOC_LS1021A || ARCH_LAYERSCAPE || \ + ARCH_SPACEMIT || COMPILE_TEST depends on HAS_IOMEM help This enables support for the Quad SPI controller in master mode. diff --git a/drivers/spi/spi-fsl-qspi.c b/drivers/spi/spi-fsl-qspi.c index 46a3187b3354..a223b4bc6e63 100644 --- a/drivers/spi/spi-fsl-qspi.c +++ b/drivers/spi/spi-fsl-qspi.c @@ -268,6 +268,16 @@ static const struct fsl_qspi_devtype_data ls2080a_data = { .little_endian = true, }; +static const struct fsl_qspi_devtype_data spacemit_k1_data = { + .rxfifo = SZ_128, + .txfifo = SZ_256, + .ahb_buf_size = SZ_512, + .sfa_size = SZ_1K, + .invalid_mstrid = QUADSPI_BUFXCR_INVALID_MSTRID, + .quirks = QUADSPI_QUIRK_TKT253890 | QUADSPI_QUIRK_SKIP_CLK_DISABLE, + .little_endian = true, +}; + struct fsl_qspi { void __iomem *iobase; void __iomem *ahb_addr; @@ -1003,6 +1013,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = { { .compatible = "fsl,imx6ul-qspi", .data = &imx6ul_data, }, { .compatible = "fsl,ls1021a-qspi", .data = &ls1021a_data, }, { .compatible = "fsl,ls2080a-qspi", .data = &ls2080a_data, }, + { .compatible = "spacemit,k1-qspi", .data = &spacemit_k1_data, }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);