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clk: samsung: clk-pll: Add support for pll_{0717x, 0718x, 0732x}

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These PLLs are found in the Exynos990 SoC. The PLLs are similar
to pll0822x.

pll0717x and pll0718x are an exception, and they use the mdiv
mask from 1718X (that is, one bit smaller).

Apart from that, the masks/shifts are identical to those of 0822x.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20241209-exynos990-cmu-v4-2-57f07080f9e4@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Igor Belwon 2024-12-09 15:45:22 +01:00 committed by Krzysztof Kozlowski
parent 5feae3e79d
commit 4a450ed26c
2 changed files with 15 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/clk/samsung/clk-pll.c
View File

@ -430,7 +430,10 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = {
#define PLL0822X_LOCK_STAT_SHIFT (29)
#define PLL0822X_ENABLE_SHIFT (31)
/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */
/*
* PLL1418x, PLL0717x and PLL0718x are similar
* to PLL0822x, except that MDIV is one bit smaller
*/
#define PLL1418X_MDIV_MASK (0x1FF)
static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
@ -441,10 +444,14 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,
u64 fvco = parent_rate;
pll_con3 = readl_relaxed(pll->con_reg);
if (pll->type != pll_1418x)
if (pll->type != pll_1418x &&
pll->type != pll_0717x &&
pll->type != pll_0718x)
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;
else
mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;
pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;
sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
@ -1377,6 +1384,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx,
case pll_0516x:
case pll_0517x:
case pll_0518x:
case pll_0717x:
case pll_0718x:
case pll_0732x:
pll->enable_offs = PLL0822X_ENABLE_SHIFT;
pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT;
if (!pll->rate_table)

3
drivers/clk/samsung/clk-pll.h
View File

@ -45,6 +45,9 @@ enum samsung_pll_type {
pll_531x,
pll_1051x,
pll_1052x,
pll_0717x,
pll_0718x,
pll_0732x,
};
#define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \