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Renesas ARM DT updates for v5.19 (take two)

Browse Source 
- I2C, sound, USB, CANFD, timer, watchdog, (Q)SPI, cpufreq, and
     thermal support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVK
     development board,
   - Initial support for the R-Car V4H SoC and the Renesas White Hawk
     development board stack,
   - DMA, RTC, and USB support for the RZ/N1D SoC,
   - Initial support for the RZ/V2M SoC an the RZ/V2M Evaluation Kit
     Board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-arm-dt-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Renesas ARM DT updates for v5.19 (take two)

  - I2C, sound, USB, CANFD, timer, watchdog, (Q)SPI, cpufreq, and
    thermal support for the RZ/G2UL SoC and the RZ/G2UL SMARC EVK
    development board,
  - Initial support for the R-Car V4H SoC and the Renesas White Hawk
    development board stack,
  - DMA, RTC, and USB support for the RZ/N1D SoC,
  - Initial support for the RZ/V2M SoC an the RZ/V2M Evaluation Kit
    Board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v5.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (40 commits)
  arm64: dts: renesas: Add initial device tree for RZ/V2M EVK
  arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC
  arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
  ARM: dts: r9a06g032: Link the PCI USB devices to the USB PHY
  ARM: dts: r9a06g032: Add USB PHY DT support
  ARM: dts: r9a06g032: Add internal PCI bridge node
  ARM: dts: r9a06g032: Describe the RTC
  arm64: dts: renesas: Add interrupt-names to CANFD nodes
  arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
  arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA
  arm64: dts: renesas: r9a07g043: Add TSU node
  arm64: dts: renesas: r9a07g043: Add OPP table
  arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
  arm64: dts: renesas: r9a07g054: Fix external clk node names
  arm64: dts: renesas: r9a07g044: Fix external clk node names
  ARM: dts: r9a06g032: Fix the NAND controller node
  ARM: dts: r9a06g032: Fill the UART DMA properties
  ARM: dts: r9a06g032: Describe the DMA router
  ARM: dts: r9a06g032: Add the two DMA nodes
  arm64: dts: renesas: Remove empty rgb output endpoints
  ...

Link: https://lore.kernel.org/r/cover.1651828603.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2022-05-06 22:30:58 +02:00
commit 4a17dc417a
39 changed files with 1570 additions and 204 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

110
arch/arm/boot/dts/r9a06g032.dtsi
View File

@ -66,6 +66,19 @@ soc {
interrupt-parent = <&gic>;
ranges;
rtc0: rtc@40006000 {
compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc";
reg = <0x40006000 0x1000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "alarm", "timer", "pps";
clocks = <&sysctrl R9A06G032_HCLK_RTC>;
clock-names = "hclk";
power-domains = <&sysctrl>;
status = "disabled";
};
wdt0: watchdog@40008000 {
compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt";
reg = <0x40008000 0x1000>;
@ -87,10 +100,62 @@ sysctrl: system-controller@4000c000 {
reg = <0x4000c000 0x1000>;
status = "okay";
#clock-cells = <1>;
#power-domain-cells = <0>;
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
#address-cells = <1>;
#size-cells = <1>;
dmamux: dma-router@a0 {
compatible = "renesas,rzn1-dmamux";
reg = <0xa0 4>;
#dma-cells = <6>;
dma-requests = <32>;
dma-masters = <&dma0 &dma1>;
};
};
pci_usb: pci@40030000 {
compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1";
device_type = "pci";
clocks = <&sysctrl R9A06G032_HCLK_USBH>,
<&sysctrl R9A06G032_HCLK_USBPM>,
<&sysctrl R9A06G032_CLK_PCI_USB>;
clock-names = "hclkh", "hclkpm", "pciclk";
power-domains = <&sysctrl>;
reg = <0x40030000 0xc00>,
<0x40020000 0x1100>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
/* Should map all possible DDR as inbound ranges, but
* the IP only supports a 256MB, 512MB, or 1GB window.
* flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
*/
dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
interrupt-map-mask = <0xf800 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
phys = <&usbphy>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x1000 0 0 0 0>;
phys = <&usbphy>;
phy-names = "usb";
};
};
uart0: serial@40060000 {
@ -134,6 +199,8 @@ uart3: serial@50000000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -145,6 +212,8 @@ uart4: serial@50001000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -156,6 +225,8 @@ uart5: serial@50002000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -167,6 +238,8 @@ uart6: serial@50003000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -178,6 +251,8 @@ uart7: serial@50004000 {
reg-io-width = <4>;
clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
clock-names = "baudclk", "apb_pclk";
dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
dma-names = "rx", "tx";
status = "disabled";
};
@ -195,11 +270,40 @@ nand_controller: nand-controller@40102000 {
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
clock-names = "hclk", "eclk";
power-domains = <&sysctrl>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dma0: dma-controller@40104000 {
compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
reg = <0x40104000 0x1000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hclk";
clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
dma-channels = <8>;
dma-requests = <16>;
dma-masters = <1>;
#dma-cells = <3>;
block_size = <0xfff>;
data-width = <8>;
};
dma1: dma-controller@40105000 {
compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma";
reg = <0x40105000 0x1000>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hclk";
clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
dma-channels = <8>;
dma-requests = <16>;
dma-masters = <1>;
#dma-cells = <3>;
block_size = <0xfff>;
data-width = <8>;
};
gic: interrupt-controller@44101000 {
compatible = "arm,gic-400", "arm,cortex-a7-gic";
interrupt-controller;
@ -224,4 +328,10 @@ timer {
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
usbphy: usb-phy {
#phy-cells = <0>;
compatible = "usb-nop-xceiv";
status = "disabled";
};
};

4
arch/arm64/boot/dts/renesas/Makefile
View File

@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb
dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb
dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb
dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb
@ -81,3 +83,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb
dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb

10
arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi
View File

@ -272,8 +272,14 @@ &can1 {
status = "okay";
};
&du_out_rgb {
remote-endpoint = <&rgb_panel>;
&du {
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&rgb_panel>;
};
};
};
};
&ehci0 {

2
arch/arm64/boot/dts/renesas/draak.dtsi
View File

@ -285,7 +285,7 @@ &du {
ports {
port@0 {
endpoint {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};

2
arch/arm64/boot/dts/renesas/ebisu.dtsi
View File

@ -356,7 +356,7 @@ &du {
ports {
port@0 {
endpoint {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};

5
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@ -1179,6 +1179,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774A1_CLK_CANFD>,
<&can_clk>;
@ -2738,8 +2739,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2776,8 +2775,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@ -1052,6 +1052,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774B1_CLK_CANFD>,
<&can_clk>;
@ -2583,8 +2584,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2621,8 +2620,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

2
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
View File

@ -172,7 +172,7 @@ &du {
ports {
port@0 {
endpoint {
du_out_rgb: endpoint {
remote-endpoint = <&tda19988_in>;
};
};

7
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@ -1009,6 +1009,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774C0_CLK_CANFD>,
<&can_clk>;
@ -1871,8 +1872,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1914,8 +1913,6 @@ lvds0_in: endpoint {
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -1941,8 +1938,6 @@ lvds1_in: endpoint {
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@ -1280,6 +1280,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A774E1_CLK_CANFD>,
<&can_clk>;
@ -2857,8 +2858,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2895,8 +2894,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@ -1368,6 +1368,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7795_CLK_CANFD>,
<&can_clk>;
@ -3351,8 +3352,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -3395,8 +3394,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@ -1240,6 +1240,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A7796_CLK_CANFD>,
<&can_clk>;
@ -2954,8 +2955,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2992,8 +2991,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View File

@ -1229,6 +1229,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77961_CLK_CANFD>,
<&can_clk>;
@ -2764,8 +2765,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2802,8 +2801,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@ -1103,6 +1103,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77965_CLK_CANFD>,
<&can_clk>;
@ -2766,8 +2767,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
reg = <1>;
@ -2804,8 +2803,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@ -557,6 +557,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77970_CLK_CANFD>,
<&can_clk>;
@ -1157,8 +1158,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1191,8 +1190,6 @@ lvds0_in: endpoint {
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

5
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@ -609,6 +609,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77980_CLK_CANFD>,
<&can_clk>;
@ -1534,8 +1535,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1569,8 +1568,6 @@ lvds0_in: endpoint {
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};

7
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -1052,6 +1052,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77990_CLK_CANFD>,
<&can_clk>;
@ -2048,8 +2049,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -2091,8 +2090,6 @@ lvds0_in: endpoint {
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -2118,8 +2115,6 @@ lvds1_in: endpoint {
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};

7
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View File

@ -557,6 +557,7 @@ canfd: can@e66c0000 {
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "ch_int", "g_int";
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
<&can_clk>;
@ -1367,8 +1368,6 @@ ports {
port@0 {
reg = <0>;
du_out_rgb: endpoint {
};
};
port@1 {
@ -1410,8 +1409,6 @@ lvds0_in: endpoint {
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
};
@ -1437,8 +1434,6 @@ lvds1_in: endpoint {
port@1 {
reg = <1>;
lvds1_out: endpoint {
};
};
};
};

74
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@ -86,7 +86,7 @@ soc: soc {
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a779a0-wdt",
"renesas,rcar-gen3-wdt";
"renesas,rcar-gen4-wdt";
reg = <0 0xe6020000 0 0x0c>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 907>;
@ -430,7 +430,7 @@ tmu4: timer@ffc00000 {
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe6500000 0 0x40>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 518>;
@ -446,7 +446,7 @@ i2c0: i2c@e6500000 {
i2c1: i2c@e6508000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 519>;
@ -462,7 +462,7 @@ i2c1: i2c@e6508000 {
i2c2: i2c@e6510000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe6510000 0 0x40>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 520>;
@ -478,7 +478,7 @@ i2c2: i2c@e6510000 {
i2c3: i2c@e66d0000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe66d0000 0 0x40>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 521>;
@ -494,7 +494,7 @@ i2c3: i2c@e66d0000 {
i2c4: i2c@e66d8000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe66d8000 0 0x40>;
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
@ -510,7 +510,7 @@ i2c4: i2c@e66d8000 {
i2c5: i2c@e66e0000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe66e0000 0 0x40>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 523>;
@ -526,7 +526,7 @@ i2c5: i2c@e66e0000 {
i2c6: i2c@e66e8000 {
compatible = "renesas,i2c-r8a779a0",
"renesas,rcar-gen3-i2c";
"renesas,rcar-gen4-i2c";
reg = <0 0xe66e8000 0 0x40>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 524>;
@ -542,7 +542,7 @@ i2c6: i2c@e66e8000 {
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6540000 0 0x60>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
@ -558,7 +558,7 @@ hscif0: serial@e6540000 {
hscif1: serial@e6550000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6550000 0 0x60>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 515>,
@ -574,7 +574,7 @@ hscif1: serial@e6550000 {
hscif2: serial@e6560000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe6560000 0 0x60>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 516>,
@ -590,7 +590,7 @@ hscif2: serial@e6560000 {
hscif3: serial@e66a0000 {
compatible = "renesas,hscif-r8a779a0",
"renesas,rcar-gen3-hscif", "renesas,hscif";
"renesas,rcar-gen4-hscif", "renesas,hscif";
reg = <0 0xe66a0000 0 0x60>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 517>,
@ -943,7 +943,7 @@ avb5: ethernet@e6850000 {
scif0: serial@e6e60000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 702>,
@ -959,7 +959,7 @@ scif0: serial@e6e60000 {
scif1: serial@e6e68000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>,
@ -975,7 +975,7 @@ scif1: serial@e6e68000 {
scif3: serial@e6c50000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6c50000 0 64>;
interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 704>,
@ -991,7 +991,7 @@ scif3: serial@e6c50000 {
scif4: serial@e6c40000 {
compatible = "renesas,scif-r8a779a0",
"renesas,rcar-gen3-scif", "renesas,scif";
"renesas,rcar-gen4-scif", "renesas,scif";
reg = <0 0xe6c40000 0 64>;
interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 705>,
@ -2003,7 +2003,8 @@ vin31isp3: endpoint@3 {
};
dmac1: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779a0";
compatible = "renesas,dmac-r8a779a0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7350000 0 0x1000>,
<0 0xe7300000 0 0x10000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
@ -2037,7 +2038,8 @@ dmac1: dma-controller@e7350000 {
};
dmac2: dma-controller@e7351000 {
compatible = "renesas,dmac-r8a779a0";
compatible = "renesas,dmac-r8a779a0",
"renesas,rcar-gen4-dmac";
reg = <0 0xe7351000 0 0x1000>,
<0 0xe7310000 0 0x10000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
@ -2092,7 +2094,8 @@ rpc: spi@ee200000 {
};
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee480000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 10>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2100,7 +2103,8 @@ ipmmu_rt0: iommu@ee480000 {
};
ipmmu_rt1: iommu@ee4c0000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 19>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2108,7 +2112,8 @@ ipmmu_rt1: iommu@ee4c0000 {
};
ipmmu_ds0: iommu@eed00000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 0>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2116,7 +2121,8 @@ ipmmu_ds0: iommu@eed00000 {
};
ipmmu_ds1: iommu@eed40000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 1>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2124,7 +2130,8 @@ ipmmu_ds1: iommu@eed40000 {
};
ipmmu_ir: iommu@eed80000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 3>;
power-domains = <&sysc R8A779A0_PD_A3IR>;
@ -2132,7 +2139,8 @@ ipmmu_ir: iommu@eed80000 {
};
ipmmu_vc0: iommu@eedc0000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeedc0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 12>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2140,7 +2148,8 @@ ipmmu_vc0: iommu@eedc0000 {
};
ipmmu_vi0: iommu@eee80000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee80000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 14>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2148,7 +2157,8 @@ ipmmu_vi0: iommu@eee80000 {
};
ipmmu_vi1: iommu@eeec0000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeeec0000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 15>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2156,7 +2166,8 @@ ipmmu_vi1: iommu@eeec0000 {
};
ipmmu_3dg: iommu@eee00000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeee00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 6>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2164,7 +2175,8 @@ ipmmu_3dg: iommu@eee00000 {
};
ipmmu_vip0: iommu@eef00000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef00000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 5>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2172,7 +2184,8 @@ ipmmu_vip0: iommu@eef00000 {
};
ipmmu_vip1: iommu@eef40000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeef40000 0 0x20000>;
renesas,ipmmu-main = <&ipmmu_mm 11>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@ -2180,7 +2193,8 @@ ipmmu_vip1: iommu@eef40000 {
};
ipmmu_mm: iommu@eefc0000 {
compatible = "renesas,ipmmu-r8a779a0";
compatible = "renesas,ipmmu-r8a779a0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeefc0000 0 0x20000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;

45
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi Normal file
View File

@ -0,0 +1,45 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the White Hawk CPU board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a779g0.dtsi"
/ {
model = "Renesas White Hawk CPU board";
compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0";
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0x0 0x48000000 0x0 0x78000000>;
};
memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
memory@600000000 {
device_type = "memory";
reg = <0x6 0x00000000 0x1 0x00000000>;
};
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&hscif0 {
status = "okay";
};
&scif_clk {
clock-frequency = <24000000>;
};

22
arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the White Hawk CPU and BreakOut boards
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a779g0-white-hawk-cpu.dtsi"
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0";
aliases {
serial0 = &hscif0;
};
chosen {
stdout-path = "serial0:921600n8";
};
};

122
arch/arm64/boot/dts/renesas/r8a779g0.dtsi Normal file
View File

@ -0,0 +1,122 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the R-Car V4H (R8A779G0) SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a779g0-sysc.h>
/ {
compatible = "renesas,r8a779g0";
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
a76_0: cpu@0 {
compatible = "arm,cortex-a76";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A779G0_PD_A1E0D0C0>;
};
};
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
extalr_clk: extalr {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
pmu_a76 {
compatible = "arm,cortex-a76-pmu";
interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779g0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <2>;
#power-domain-cells = <0>;
#reset-cells = <1>;
};
rst: reset-controller@e6160000 {
compatible = "renesas,r8a779g0-rst";
reg = <0 0xe6160000 0 0x4000>;
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a779g0-sysc";
reg = <0 0xe6180000 0 0x4000>;
#power-domain-cells = <1>;
};
hscif0: serial@e6540000 {
compatible = "renesas,hscif-r8a779g0",
"renesas,rcar-gen4-hscif",
"renesas,hscif";
reg = <0 0xe6540000 0 96>;
interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 514>,
<&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 514>;
status = "disabled";
};
gic: interrupt-controller@f1000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0xf1000000 0 0x20000>,
<0x0 0xf1060000 0 0x110000>;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

444
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@ -42,6 +42,33 @@ extal_clk: extal-clk {
clock-frequency = <0>;
};
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-125000000 {
opp-hz = /bits/ 64 <125000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-250000000 {
opp-hz = /bits/ 64 <250000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1100000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -50,9 +77,11 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
#cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
@ -75,16 +104,135 @@ soc: soc {
ranges;
ssi0: ssi@10049c00 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x10049c00 0 0x400>;
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
dmas = <&dmac 0x2655>, <&dmac 0x2656>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
/* place holder */
status = "disabled";
};
ssi1: ssi@1004a000 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a000 0 0x400>;
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
dmas = <&dmac 0x2659>, <&dmac 0x265a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi2: ssi@1004a400 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a400 0 0x400>;
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
dmas = <&dmac 0x265f>;
dma-names = "rt";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
ssi3: ssi@1004a800 {
compatible = "renesas,r9a07g043-ssi",
"renesas,rz-ssi";
reg = <0 0x1004a800 0 0x400>;
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
<&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
<&audio_clk1>, <&audio_clk2>;
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
dmas = <&dmac 0x2661>, <&dmac 0x2662>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
#sound-dai-cells = <0>;
status = "disabled";
};
spi0: spi@1004ac00 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004ac00 0 0x400>;
interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
resets = <&cpg R9A07G043_RSPI0_RST>;
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@1004b000 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
resets = <&cpg R9A07G043_RSPI1_RST>;
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
status = "disabled";
};
spi2: spi@1004b400 {
compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b400 0 0x400>;
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
resets = <&cpg R9A07G043_RSPI2_RST>;
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
scif0: serial@1004b800 {
@ -213,29 +361,125 @@ sci1: serial@1004d400 {
};
canfd: can@10050000 {
compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
reg = <0 0x10050000 0 0x8000>;
/* place holder */
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "g_err", "g_recc",
"ch0_err", "ch0_rec", "ch0_trx",
"ch1_err", "ch1_rec", "ch1_trx";
clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
<&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
assigned-clock-rates = <50000000>;
resets = <&cpg R9A07G043_CANFD_RSTP_N>,
<&cpg R9A07G043_CANFD_RSTC_N>;
reset-names = "rstp_n", "rstc_n";
power-domains = <&cpg>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
i2c0: i2c@10058000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058000 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G043_I2C0_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
i2c1: i2c@10058400 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058400 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G043_I2C1_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
i2c2: i2c@10058800 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058800 0 0x400>;
interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G043_I2C2_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
i2c3: i2c@10058c00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
reg = <0 0x10058c00 0 0x400>;
/* place holder */
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tei", "ri", "ti", "spi", "sti",
"naki", "ali", "tmoi";
clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
clock-frequency = <100000>;
resets = <&cpg R9A07G043_I2C3_MRST>;
power-domains = <&cpg>;
status = "disabled";
};
adc: adc@10059000 {
@ -243,13 +487,30 @@ adc: adc@10059000 {
/* place holder */
};
tsu: thermal@10059400 {
compatible = "renesas,r9a07g043-tsu",
"renesas,rzg2l-tsu";
reg = <0 0x10059400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
resets = <&cpg R9A07G043_TSU_PRESETN>;
power-domains = <&cpg>;
#thermal-sensor-cells = <1>;
};
sbc: spi@10060000 {
compatible = "renesas,r9a07g043-rpc-if",
"renesas,rzg2l-rpc-if";
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
reg-names = "regs", "dirmap", "wbuf";
clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
<&cpg CPG_MOD R9A07G043_SPI_CLK>;
resets = <&cpg R9A07G043_SPI_RST>;
power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
/* place holder */
status = "disabled";
};
cpg: clock-controller@11010000 {
@ -406,68 +667,211 @@ eth1: ethernet@11c30000 {
};
phyrst: usbphy-ctrl@11c40000 {
compatible = "renesas,r9a07g043-usbphy-ctrl",
"renesas,rzg2l-usbphy-ctrl";
reg = <0 0x11c40000 0 0x10000>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
resets = <&cpg R9A07G043_USB_PRESETN>;
power-domains = <&cpg>;
#reset-cells = <1>;
status = "disabled";
};
ohci0: usb@11c50000 {
compatible = "generic-ohci";
reg = <0 0x11c50000 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
<&cpg R9A07G043_USB_U2H0_HRESETN>;
phys = <&usb2_phy0 1>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
ohci1: usb@11c70000 {
compatible = "generic-ohci";
reg = <0 0x11c70000 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
<&cpg R9A07G043_USB_U2H1_HRESETN>;
phys = <&usb2_phy1 1>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
ehci0: usb@11c50100 {
compatible = "generic-ehci";
reg = <0 0x11c50100 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>,
<&cpg R9A07G043_USB_U2H0_HRESETN>;
phys = <&usb2_phy0 2>;
phy-names = "usb";
companion = <&ohci0>;
power-domains = <&cpg>;
status = "disabled";
};
ehci1: usb@11c70100 {
compatible = "generic-ehci";
reg = <0 0x11c70100 0 0x100>;
/* place holder */
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>,
<&cpg R9A07G043_USB_U2H1_HRESETN>;
phys = <&usb2_phy1 2>;
phy-names = "usb";
companion = <&ohci1>;
power-domains = <&cpg>;
status = "disabled";
};
usb2_phy0: usb-phy@11c50200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c50200 0 0x700>;
/* place holder */
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
resets = <&phyrst 0>;
#phy-cells = <1>;
power-domains = <&cpg>;
status = "disabled";
};
usb2_phy1: usb-phy@11c70200 {
compatible = "renesas,usb2-phy-r9a07g043",
"renesas,rzg2l-usb2-phy";
reg = <0 0x11c70200 0 0x700>;
/* place holder */
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
resets = <&phyrst 1>;
#phy-cells = <1>;
power-domains = <&cpg>;
status = "disabled";
};
hsusb: usb@11c60000 {
compatible = "renesas,usbhs-r9a07g043",
"renesas,rza2-usbhs";
reg = <0 0x11c60000 0 0x10000>;
/* place holder */
interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
<&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
resets = <&phyrst 0>,
<&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
renesas,buswait = <7>;
phys = <&usb2_phy0 3>;
phy-names = "usb";
power-domains = <&cpg>;
status = "disabled";
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a07g043-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g043-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
/* place holder */
clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G043_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G043_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801000 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
ostm1: timer@12801400 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801400 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
ostm2: timer@12801800 {
compatible = "renesas,r9a07g043-ostm",
"renesas,ostm";
reg = <0x0 0x12801800 0x0 0x400>;
/* place holder */
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
power-domains = <&cpg>;
status = "disabled";
};
};
thermal-zones {
cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsu 0>;
sustainable-power = <717>;
cooling-maps {
map0 {
trip = <&target>;
cooling-device = <&cpu0 0 2>;
contribution = <1024>;
};
};
trips {
sensor_crit: sensor-crit {
temperature = <125000>;
hysteresis = <1000>;
type = "critical";
};
target: trip-point {
temperature = <100000>;
hysteresis = <1000>;
type = "passive";
};
};
};
};

76
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
View File

@ -14,84 +14,8 @@ / {
compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
};
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ehci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&hsusb {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&i2c1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
&ohci0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ohci1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&phyrst {
status = "disabled";
};
&spi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&ssi0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy0 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
&usb2_phy1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};

8
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@ -13,14 +13,14 @@ / {
#address-cells = <2>;
#size-cells = <2>;
audio_clk1: audio_clk1 {
audio_clk1: audio1-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
audio_clk2: audio_clk2 {
audio_clk2: audio2-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
@ -28,14 +28,14 @@ audio_clk2: audio_clk2 {
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
can_clk: can-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */

8
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@ -13,14 +13,14 @@ / {
#address-cells = <2>;
#size-cells = <2>;
audio_clk1: audio_clk1 {
audio_clk1: audio1-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
audio_clk2: audio_clk2 {
audio_clk2: audio2-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
@ -28,14 +28,14 @@ audio_clk2: audio_clk2 {
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
can_clk: can-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */

44
arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts Normal file
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@ -0,0 +1,44 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r9a09g011.dtsi"
/ {
model = "RZ/V2M Evaluation Kit 2.0";
compatible = "renesas,rzv2mevk2", "renesas,r9a09g011";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
memory@58000000 {
device_type = "memory";
/*
* first 1.25GiB is reserved for ISP Firmware,
* next 128MiB is reserved for secure area.
*/
reg = <0x0 0x58000000 0x0 0x28000000>;
};
memory@180000000 {
device_type = "memory";
reg = <0x1 0x80000000 0x0 0x80000000>;
};
};
&extal_clk {
clock-frequency = <48000000>;
};
&uart0 {
status = "okay";
};

93
arch/arm64/boot/dts/renesas/r9a09g011.dtsi Normal file
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@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2M SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a09g011-cpg.h>
/ {
compatible = "renesas,r9a09g011";
#address-cells = <2>;
#size-cells = <2>;
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
};
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@82000000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x82010000 0 0x1000>,
<0x0 0x82020000 0 0x20000>,
<0x0 0x82040000 0 0x20000>,
<0x0 0x82060000 0 0x20000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
clock-names = "clk";
};
cpg: clock-controller@a3500000 {
compatible = "renesas,r9a09g011-cpg";
reg = <0 0xa3500000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
uart0: serial@a4040000 {
compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
reg = <0 0xa4040000 0 0x80>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
<&cpg CPG_MOD R9A09G011_URT_PCLK>;
clock-names = "sclk", "pclk";
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};

8
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
View File

@ -52,7 +52,6 @@ snd_rzg2l: sound {
"Mic Bias", "Microphone Jack";
cpu_dai: simple-audio-card,cpu {
sound-dai = <&ssi0>;
};
codec_dai: simple-audio-card,codec {
@ -168,13 +167,6 @@ &spi1 {
status = "okay";
};
&ssi0 {
pinctrl-0 = <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";

11
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
View File

@ -18,6 +18,10 @@ aliases {
};
};
&cpu_dai {
sound-dai = <&ssi0>;
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
@ -49,6 +53,13 @@ &scif2 {
};
#endif
&ssi0 {
pinctrl-0 = <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
&vccq_sdhi1 {
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
};

11
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
View File

@ -60,6 +60,10 @@ &canfd {
};
#endif
&cpu_dai {
sound-dai = <&ssi0>;
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
@ -91,6 +95,13 @@ &scif1 {
};
#endif
&ssi0 {
pinctrl-0 = <&ssi0_pins>;
pinctrl-names = "default";
status = "okay";
};
#if (SW_RSPI_CAN)
&spi1 {
/delete-property/ pinctrl-0;

56
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
View File

@ -12,6 +12,44 @@ &pinctrl {
pinctrl-0 = <&sound_clk_pins>;
pinctrl-names = "default";
can0_pins: can0 {
pinmux = <RZG2L_PORT_PINMUX(1, 1, 3)>, /* TX */
<RZG2L_PORT_PINMUX(1, 2, 3)>; /* RX */
};
#if (SW_ET0_EN_N)
can0-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can0_stb";
};
#endif
can1_pins: can1 {
pinmux = <RZG2L_PORT_PINMUX(2, 0, 3)>, /* TX */
<RZG2L_PORT_PINMUX(2, 1, 3)>; /* RX */
};
#if (SW_ET0_EN_N)
can1-stb-hog {
gpio-hog;
gpios = <RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
output-low;
line-name = "can1_stb";
};
#endif
i2c0_pins: i2c0 {
pins = "RIIC0_SDA", "RIIC0_SCL";
input-enable;
};
i2c1_pins: i2c1 {
pins = "RIIC1_SDA", "RIIC1_SCL";
input-enable;
};
scif0_pins: scif0 {
pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
<RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
@ -60,4 +98,22 @@ sound_clk_pins: sound_clk {
pins = "AUDIO_CLK1", "AUDIO_CLK2";
input-enable;
};
ssi1_pins: ssi1 {
pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */
<RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */
<RZG2L_PORT_PINMUX(3, 2, 2)>, /* TXD */
<RZG2L_PORT_PINMUX(3, 3, 2)>; /* RXD */
};
usb0_pins: usb0 {
pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
<RZG2L_PORT_PINMUX(5, 2, 1)>, /* OVC */
<RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
};
usb1_pins: usb1 {
pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
<RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
};
};

18
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
View File

@ -115,6 +115,14 @@ &extal_clk {
clock-frequency = <24000000>;
};
&ostm1 {
status = "okay";
};
&ostm2 {
status = "okay";
};
&pinctrl {
eth0_pins: eth0 {
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
@ -231,3 +239,13 @@ &sdhi0 {
status = "okay";
};
#endif
&wdt0 {
status = "okay";
timeout-sec = <60>;
};
&wdt2 {
status = "okay";
timeout-sec = <60>;
};

39
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
View File

@ -19,6 +19,45 @@
#include "rzg2ul-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"
#if (!SW_ET0_EN_N)
&canfd {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
#endif
&cpu_dai {
sound-dai = <&ssi1>;
};
&i2c1 {
wm8978: codec@1a {
compatible = "wlf,wm8978";
#sound-dai-cells = <0>;
reg = <0x1a>;
};
};
#if (SW_ET0_EN_N)
&ssi1 {
pinctrl-0 = <&ssi1_pins>;
pinctrl-names = "default";
status = "okay";
};
#else
&snd_rzg2l {
status = "disabled";
};
&ssi1 {
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
status = "disabled";
};
#endif
&vccq_sdhi1 {
gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>;
};

2
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@ -386,7 +386,7 @@ &du {
ports {
port@0 {
endpoint {
du_out_rgb: endpoint {
remote-endpoint = <&adv7123_in>;
};
};

10
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View File

@ -97,8 +97,14 @@ &can1 {
status = "okay";
};
&du_out_rgb {
remote-endpoint = <&adv7513_in>;
&du {
ports {
port@0 {
du_out_rgb: endpoint {
remote-endpoint = <&adv7513_in>;
};
};
};
};
&ehci0 {

90
include/dt-bindings/clock/r8a779g0-cpg-mssr.h Normal file
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@ -0,0 +1,90 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* r8a779g0 CPG Core Clocks */
#define R8A779G0_CLK_ZX 0
#define R8A779G0_CLK_ZS 1
#define R8A779G0_CLK_ZT 2
#define R8A779G0_CLK_ZTR 3
#define R8A779G0_CLK_S0D2 4
#define R8A779G0_CLK_S0D3 5
#define R8A779G0_CLK_S0D4 6
#define R8A779G0_CLK_S0D1_VIO 7
#define R8A779G0_CLK_S0D2_VIO 8
#define R8A779G0_CLK_S0D4_VIO 9
#define R8A779G0_CLK_S0D8_VIO 10
#define R8A779G0_CLK_S0D1_VC 11
#define R8A779G0_CLK_S0D2_VC 12
#define R8A779G0_CLK_S0D4_VC 13
#define R8A779G0_CLK_S0D2_MM 14
#define R8A779G0_CLK_S0D4_MM 15
#define R8A779G0_CLK_S0D2_U3DG 16
#define R8A779G0_CLK_S0D4_U3DG 17
#define R8A779G0_CLK_S0D2_RT 18
#define R8A779G0_CLK_S0D3_RT 19
#define R8A779G0_CLK_S0D4_RT 20
#define R8A779G0_CLK_S0D6_RT 21
#define R8A779G0_CLK_S0D24_RT 22
#define R8A779G0_CLK_S0D2_PER 23
#define R8A779G0_CLK_S0D3_PER 24
#define R8A779G0_CLK_S0D4_PER 25
#define R8A779G0_CLK_S0D6_PER 26
#define R8A779G0_CLK_S0D12_PER 27
#define R8A779G0_CLK_S0D24_PER 28
#define R8A779G0_CLK_S0D1_HSC 29
#define R8A779G0_CLK_S0D2_HSC 30
#define R8A779G0_CLK_S0D4_HSC 31
#define R8A779G0_CLK_S0D2_CC 32
#define R8A779G0_CLK_SVD1_IR 33
#define R8A779G0_CLK_SVD2_IR 34
#define R8A779G0_CLK_SVD1_VIP 35
#define R8A779G0_CLK_SVD2_VIP 36
#define R8A779G0_CLK_CL 37
#define R8A779G0_CLK_CL16M 38
#define R8A779G0_CLK_CL16M_MM 39
#define R8A779G0_CLK_CL16M_RT 40
#define R8A779G0_CLK_CL16M_PER 41
#define R8A779G0_CLK_CL16M_HSC 42
#define R8A779G0_CLK_Z0 43
#define R8A779G0_CLK_ZB3 44
#define R8A779G0_CLK_ZB3D2 45
#define R8A779G0_CLK_ZB3D4 46
#define R8A779G0_CLK_ZG 47
#define R8A779G0_CLK_SD0H 48
#define R8A779G0_CLK_SD0 49
#define R8A779G0_CLK_RPC 50
#define R8A779G0_CLK_RPCD2 51
#define R8A779G0_CLK_MSO 52
#define R8A779G0_CLK_CANFD 53
#define R8A779G0_CLK_CSI 54
#define R8A779G0_CLK_FRAY 55
#define R8A779G0_CLK_IPC 56
#define R8A779G0_CLK_SASYNCRT 57
#define R8A779G0_CLK_SASYNCPERD1 58
#define R8A779G0_CLK_SASYNCPERD2 59
#define R8A779G0_CLK_SASYNCPERD4 60
#define R8A779G0_CLK_VIOBUS 61
#define R8A779G0_CLK_VIOBUSD2 62
#define R8A779G0_CLK_VCBUS 63
#define R8A779G0_CLK_VCBUSD2 64
#define R8A779G0_CLK_DSIEXT 65
#define R8A779G0_CLK_DSIREF 66
#define R8A779G0_CLK_ADGH 67
#define R8A779G0_CLK_OSC 68
#define R8A779G0_CLK_ZR0 69
#define R8A779G0_CLK_ZR1 70
#define R8A779G0_CLK_ZR2 71
#define R8A779G0_CLK_IMPA 72
#define R8A779G0_CLK_IMPAD4 73
#define R8A779G0_CLK_CPEX 74
#define R8A779G0_CLK_CBFUSA 75
#define R8A779G0_CLK_R 76
#endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */

352
include/dt-bindings/clock/r9a09g011-cpg.h Normal file
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@ -0,0 +1,352 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
#define __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__
#include <dt-bindings/clock/renesas-cpg-mssr.h>
/* Module Clocks */
#define R9A09G011_SYS_CLK 0
#define R9A09G011_PFC_PCLK 1
#define R9A09G011_PMC_CORE_CLOCK 2
#define R9A09G011_GIC_CLK 3
#define R9A09G011_RAMA_ACLK 4
#define R9A09G011_ROMA_ACLK 5
#define R9A09G011_SEC_ACLK 6
#define R9A09G011_SEC_PCLK 7
#define R9A09G011_SEC_TCLK 8
#define R9A09G011_DMAA_ACLK 9
#define R9A09G011_TSU0_PCLK 10
#define R9A09G011_TSU1_PCLK 11
#define R9A09G011_CST_TRACECLK 12
#define R9A09G011_CST_SB_CLK 13
#define R9A09G011_CST_AHB_CLK 14
#define R9A09G011_CST_ATB_SB_CLK 15
#define R9A09G011_CST_TS_SB_CLK 16
#define R9A09G011_SDI0_ACLK 17
#define R9A09G011_SDI0_IMCLK 18
#define R9A09G011_SDI0_IMCLK2 19
#define R9A09G011_SDI0_CLK_HS 20
#define R9A09G011_SDI1_ACLK 21
#define R9A09G011_SDI1_IMCLK 22
#define R9A09G011_SDI1_IMCLK2 23
#define R9A09G011_SDI1_CLK_HS 24
#define R9A09G011_EMM_ACLK 25
#define R9A09G011_EMM_IMCLK 26
#define R9A09G011_EMM_IMCLK2 27
#define R9A09G011_EMM_CLK_HS 28
#define R9A09G011_NFI_ACLK 29
#define R9A09G011_NFI_NF_CLK 30
#define R9A09G011_PCI_ACLK 31
#define R9A09G011_PCI_CLK_PMU 32
#define R9A09G011_PCI_APB_CLK 33
#define R9A09G011_USB_ACLK_H 34
#define R9A09G011_USB_ACLK_P 35
#define R9A09G011_USB_PCLK 36
#define R9A09G011_ETH0_CLK_AXI 37
#define R9A09G011_ETH0_CLK_CHI 38
#define R9A09G011_ETH0_GPTP_EXT 39
#define R9A09G011_SDT_CLK 40
#define R9A09G011_SDT_CLKAPB 41
#define R9A09G011_SDT_CLK48 42
#define R9A09G011_GRP_CLK 43
#define R9A09G011_CIF_P0_CLK 44
#define R9A09G011_CIF_P1_CLK 45
#define R9A09G011_CIF_APB_CLK 46
#define R9A09G011_DCI_CLKAXI 47
#define R9A09G011_DCI_CLKAPB 48
#define R9A09G011_DCI_CLKDCI2 49
#define R9A09G011_HMI_PCLK 50
#define R9A09G011_LCI_PCLK 51
#define R9A09G011_LCI_ACLK 52
#define R9A09G011_LCI_VCLK 53
#define R9A09G011_LCI_LPCLK 54
#define R9A09G011_AUI_CLK 55
#define R9A09G011_AUI_CLKAXI 56
#define R9A09G011_AUI_CLKAPB 57
#define R9A09G011_AUMCLK 58
#define R9A09G011_GMCLK0 59
#define R9A09G011_GMCLK1 60
#define R9A09G011_MTR_CLK0 61
#define R9A09G011_MTR_CLK1 62
#define R9A09G011_MTR_CLKAPB 63
#define R9A09G011_GFT_CLK 64
#define R9A09G011_GFT_CLKAPB 65
#define R9A09G011_GFT_MCLK 66
#define R9A09G011_ATGA_CLK 67
#define R9A09G011_ATGA_CLKAPB 68
#define R9A09G011_ATGB_CLK 69
#define R9A09G011_ATGB_CLKAPB 70
#define R9A09G011_SYC_CNT_CLK 71
#define R9A09G011_CPERI_GRPA_PCLK 72
#define R9A09G011_TIM0_CLK 73
#define R9A09G011_TIM1_CLK 74
#define R9A09G011_TIM2_CLK 75
#define R9A09G011_TIM3_CLK 76
#define R9A09G011_TIM4_CLK 77
#define R9A09G011_TIM5_CLK 78
#define R9A09G011_TIM6_CLK 79
#define R9A09G011_TIM7_CLK 80
#define R9A09G011_IIC_PCLK0 81
#define R9A09G011_CPERI_GRPB_PCLK 82
#define R9A09G011_TIM8_CLK 83
#define R9A09G011_TIM9_CLK 84
#define R9A09G011_TIM10_CLK 85
#define R9A09G011_TIM11_CLK 86
#define R9A09G011_TIM12_CLK 87
#define R9A09G011_TIM13_CLK 88
#define R9A09G011_TIM14_CLK 89
#define R9A09G011_TIM15_CLK 90
#define R9A09G011_IIC_PCLK1 91
#define R9A09G011_CPERI_GRPC_PCLK 92
#define R9A09G011_TIM16_CLK 93
#define R9A09G011_TIM17_CLK 94
#define R9A09G011_TIM18_CLK 95
#define R9A09G011_TIM19_CLK 96
#define R9A09G011_TIM20_CLK 97
#define R9A09G011_TIM21_CLK 98
#define R9A09G011_TIM22_CLK 99
#define R9A09G011_TIM23_CLK 100
#define R9A09G011_WDT0_PCLK 101
#define R9A09G011_WDT0_CLK 102
#define R9A09G011_WDT1_PCLK 103
#define R9A09G011_WDT1_CLK 104
#define R9A09G011_CPERI_GRPD_PCLK 105
#define R9A09G011_TIM24_CLK 106
#define R9A09G011_TIM25_CLK 107
#define R9A09G011_TIM26_CLK 108
#define R9A09G011_TIM27_CLK 109
#define R9A09G011_TIM28_CLK 110
#define R9A09G011_TIM29_CLK 111
#define R9A09G011_TIM30_CLK 112
#define R9A09G011_TIM31_CLK 113
#define R9A09G011_CPERI_GRPE_PCLK 114
#define R9A09G011_PWM0_CLK 115
#define R9A09G011_PWM1_CLK 116
#define R9A09G011_PWM2_CLK 117
#define R9A09G011_PWM3_CLK 118
#define R9A09G011_PWM4_CLK 119
#define R9A09G011_PWM5_CLK 120
#define R9A09G011_PWM6_CLK 121
#define R9A09G011_PWM7_CLK 122
#define R9A09G011_CPERI_GRPF_PCLK 123
#define R9A09G011_PWM8_CLK 124
#define R9A09G011_PWM9_CLK 125
#define R9A09G011_PWM10_CLK 126
#define R9A09G011_PWM11_CLK 127
#define R9A09G011_PWM12_CLK 128
#define R9A09G011_PWM13_CLK 129
#define R9A09G011_PWM14_CLK 130
#define R9A09G011_PWM15_CLK 131
#define R9A09G011_CPERI_GRPG_PCLK 132
#define R9A09G011_CPERI_GRPH_PCLK 133
#define R9A09G011_URT_PCLK 134
#define R9A09G011_URT0_CLK 135
#define R9A09G011_URT1_CLK 136
#define R9A09G011_CSI0_CLK 137
#define R9A09G011_CSI1_CLK 138
#define R9A09G011_CSI2_CLK 139
#define R9A09G011_CSI3_CLK 140
#define R9A09G011_CSI4_CLK 141
#define R9A09G011_CSI5_CLK 142
#define R9A09G011_ICB_ACLK1 143
#define R9A09G011_ICB_GIC_CLK 144
#define R9A09G011_ICB_MPCLK1 145
#define R9A09G011_ICB_SPCLK1 146
#define R9A09G011_ICB_CLK48 147
#define R9A09G011_ICB_CLK48_2 148
#define R9A09G011_ICB_CLK48_3 149
#define R9A09G011_ICB_CLK48_4L 150
#define R9A09G011_ICB_CLK48_4R 151
#define R9A09G011_ICB_CLK48_5 152
#define R9A09G011_ICB_CST_ATB_SB_CLK 153
#define R9A09G011_ICB_CST_CS_CLK 154
#define R9A09G011_ICB_CLK100_1 155
#define R9A09G011_ICB_ETH0_CLK_AXI 156
#define R9A09G011_ICB_DCI_CLKAXI 157
#define R9A09G011_ICB_SYC_CNT_CLK 158
#define R9A09G011_ICB_DRPA_ACLK 159
#define R9A09G011_ICB_RFX_ACLK 160
#define R9A09G011_ICB_RFX_PCLK5 161
#define R9A09G011_ICB_MMC_ACLK 162
#define R9A09G011_ICB_MPCLK3 163
#define R9A09G011_ICB_CIMA_CLK 164
#define R9A09G011_ICB_CIMB_CLK 165
#define R9A09G011_ICB_BIMA_CLK 166
#define R9A09G011_ICB_FCD_CLKAXI 167
#define R9A09G011_ICB_VD_ACLK4 168
#define R9A09G011_ICB_MPCLK4 169
#define R9A09G011_ICB_VCD_PCLK4 170
#define R9A09G011_CA53_CLK 171
#define R9A09G011_CA53_ACLK 172
#define R9A09G011_CA53_APCLK_DBG 173
#define R9A09G011_CST_APB_CA53_CLK 174
#define R9A09G011_CA53_ATCLK 175
#define R9A09G011_CST_CS_CLK 176
#define R9A09G011_CA53_TSCLK 177
#define R9A09G011_CST_TS_CLK 178
#define R9A09G011_CA53_APCLK_REG 179
#define R9A09G011_DRPA_ACLK 180
#define R9A09G011_DRPA_DCLK 181
#define R9A09G011_DRPA_INITCLK 182
#define R9A09G011_RAMB0_ACLK 183
#define R9A09G011_RAMB1_ACLK 184
#define R9A09G011_RAMB2_ACLK 185
#define R9A09G011_RAMB3_ACLK 186
#define R9A09G011_CIMA_CLKAPB 187
#define R9A09G011_CIMA_CLK 188
#define R9A09G011_CIMB_CLK 189
#define R9A09G011_FAFA_CLK 190
#define R9A09G011_STG_CLKAXI 191
#define R9A09G011_STG_CLK0 192
#define R9A09G011_BIMA_CLKAPB 193
#define R9A09G011_BIMA_CLK 194
#define R9A09G011_FAFB_CLK 195
#define R9A09G011_FCD_CLK 196
#define R9A09G011_FCD_CLKAXI 197
#define R9A09G011_RIM_CLK 198
#define R9A09G011_VCD_ACLK 199
#define R9A09G011_VCD_PCLK 200
#define R9A09G011_JPG0_CLK 201
#define R9A09G011_JPG0_ACLK 202
#define R9A09G011_MMC_CORE_DDRC_CLK 203
#define R9A09G011_MMC_ACLK 204
#define R9A09G011_MMC_PCLK 205
#define R9A09G011_DDI_APBCLK 206
/* Resets */
#define R9A09G011_SYS_RST_N 0
#define R9A09G011_PFC_PRESETN 1
#define R9A09G011_RAMA_ARESETN 2
#define R9A09G011_ROM_ARESETN 3
#define R9A09G011_DMAA_ARESETN 4
#define R9A09G011_SEC_ARESETN 5
#define R9A09G011_SEC_PRESETN 6
#define R9A09G011_SEC_RSTB 7
#define R9A09G011_TSU0_RESETN 8
#define R9A09G011_TSU1_RESETN 9
#define R9A09G011_PMC_RESET_N 10
#define R9A09G011_CST_NTRST 11
#define R9A09G011_CST_NPOTRST 12
#define R9A09G011_CST_NTRST2 13
#define R9A09G011_CST_CS_RESETN 14
#define R9A09G011_CST_TS_RESETN 15
#define R9A09G011_CST_TRESETN 16
#define R9A09G011_CST_SB_RESETN 17
#define R9A09G011_CST_AHB_RESETN 18
#define R9A09G011_CST_TS_SB_RESETN 19
#define R9A09G011_CST_APB_CA53_RESETN 20
#define R9A09G011_CST_ATB_SB_RESETN 21
#define R9A09G011_SDI0_IXRST 22
#define R9A09G011_SDI1_IXRST 23
#define R9A09G011_EMM_IXRST 24
#define R9A09G011_NFI_MARESETN 25
#define R9A09G011_NFI_REG_RST_N 26
#define R9A09G011_USB_PRESET_N 27
#define R9A09G011_USB_DRD_RESET 28
#define R9A09G011_USB_ARESETN_P 29
#define R9A09G011_USB_ARESETN_H 30
#define R9A09G011_ETH0_RST_HW_N 31
#define R9A09G011_PCI_ARESETN 32
#define R9A09G011_SDT_RSTSYSAX 33
#define R9A09G011_GRP_RESETN 34
#define R9A09G011_CIF_RST_N 35
#define R9A09G011_DCU_RSTSYSAX 36
#define R9A09G011_HMI_RST_N 37
#define R9A09G011_HMI_PRESETN 38
#define R9A09G011_LCI_PRESETN 39
#define R9A09G011_LCI_ARESETN 40
#define R9A09G011_AUI_RSTSYSAX 41
#define R9A09G011_MTR_RSTSYSAX 42
#define R9A09G011_GFT_RSTSYSAX 43
#define R9A09G011_ATGA_RSTSYSAX 44
#define R9A09G011_ATGB_RSTSYSAX 45
#define R9A09G011_SYC_RST_N 46
#define R9A09G011_TIM_GPA_PRESETN 47
#define R9A09G011_TIM_GPB_PRESETN 48
#define R9A09G011_TIM_GPC_PRESETN 49
#define R9A09G011_TIM_GPD_PRESETN 50
#define R9A09G011_PWM_GPE_PRESETN 51
#define R9A09G011_PWM_GPF_PRESETN 52
#define R9A09G011_CSI_GPG_PRESETN 53
#define R9A09G011_CSI_GPH_PRESETN 54
#define R9A09G011_IIC_GPA_PRESETN 55
#define R9A09G011_IIC_GPB_PRESETN 56
#define R9A09G011_URT_PRESETN 57
#define R9A09G011_WDT0_PRESETN 58
#define R9A09G011_WDT1_PRESETN 59
#define R9A09G011_ICB_PD_AWO_RST_N 60
#define R9A09G011_ICB_PD_MMC_RST_N 61
#define R9A09G011_ICB_PD_VD0_RST_N 62
#define R9A09G011_ICB_PD_VD1_RST_N 63
#define R9A09G011_ICB_PD_RFX_RST_N 64
#define R9A09G011_CA53_NCPUPORESET0 65
#define R9A09G011_CA53_NCPUPORESET1 66
#define R9A09G011_CA53_NCORERESET0 67
#define R9A09G011_CA53_NCORERESET1 68
#define R9A09G011_CA53_NPRESETDBG 69
#define R9A09G011_CA53_L2RESET 70
#define R9A09G011_CA53_NMISCRESET_HM 71
#define R9A09G011_CA53_NMISCRESET_SM 72
#define R9A09G011_CA53_NARESET 73
#define R9A09G011_DRPA_ARESETN 74
#define R9A09G011_RAMB0_ARESETN 75
#define R9A09G011_RAMB1_ARESETN 76
#define R9A09G011_RAMB2_ARESETN 77
#define R9A09G011_RAMB3_ARESETN 78
#define R9A09G011_CIMA_RSTSYSAX 79
#define R9A09G011_CIMB_RSTSYSAX 80
#define R9A09G011_FAFA_RSTSYSAX 81
#define R9A09G011_STG_RSTSYSAX 82
#define R9A09G011_BIMA_RSTSYSAX 83
#define R9A09G011_FAFB_RSTSYSAX 84
#define R9A09G011_FCD_RSTSYSAX 85
#define R9A09G011_RIM_RSTSYSAX 86
#define R9A09G011_VCD_RESETN 87
#define R9A09G011_JPG_XRESET 88
#define R9A09G011_MMC_CORE_DDRC_RSTN 89
#define R9A09G011_MMC_ARESETN_N 90
#define R9A09G011_MMC_PRESETN 91
#define R9A09G011_DDI_PWROK 92
#define R9A09G011_DDI_RESET 93
#define R9A09G011_DDI_RESETN_APB 94
#endif /* __DT_BINDINGS_CLOCK_R9A09G011_CPG_H__ */

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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
#define __DT_BINDINGS_POWER_R8A779G0_SYSC_H__
/*
* These power domain indices match the Power Domain Register Numbers (PDR)
*/
#define R8A779G0_PD_A1E0D0C0 0
#define R8A779G0_PD_A1E0D0C1 1
#define R8A779G0_PD_A1E0D1C0 2
#define R8A779G0_PD_A1E0D1C1 3
#define R8A779G0_PD_A2E0D0 16
#define R8A779G0_PD_A2E0D1 17
#define R8A779G0_PD_A3E0 20
#define R8A779G0_PD_A33DGA 24
#define R8A779G0_PD_A23DGB 25
#define R8A779G0_PD_A1DSP0 33
#define R8A779G0_PD_A2IMP01 34
#define R8A779G0_PD_A2PSC 35
#define R8A779G0_PD_A2CV0 36
#define R8A779G0_PD_A2CV1 37
#define R8A779G0_PD_A1CNN0 41
#define R8A779G0_PD_A2CN0 42
#define R8A779G0_PD_A3IR 43
#define R8A779G0_PD_A1DSP1 45
#define R8A779G0_PD_A2IMP23 46
#define R8A779G0_PD_A2DMA 47
#define R8A779G0_PD_A2CV2 48
#define R8A779G0_PD_A2CV3 49
#define R8A779G0_PD_A1DSP2 53
#define R8A779G0_PD_A1DSP3 54
#define R8A779G0_PD_A3VIP0 56
#define R8A779G0_PD_A3VIP1 57
#define R8A779G0_PD_A3VIP2 58
#define R8A779G0_PD_A3ISP0 60
#define R8A779G0_PD_A3ISP1 61
/* Always-on power area */
#define R8A779G0_PD_ALWAYS_ON 64
#endif /* __DT_BINDINGS_POWER_R8A779G0_SYSC_H__*/