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support dma transfer for spi
This commit is contained in:
cmc
parent
ce9b786556
commit
4a0f8a94e0
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@ -557,8 +557,10 @@ static struct platform_device *devices[] __initdata = {
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#ifdef CONFIG_UART1_RK29
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&rk29_device_uart1,
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#endif
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#ifdef CONFIG_SPIM_RK29XX
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#ifdef CONFIG_SPIM0_RK29
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&rk29xx_device_spi0m,
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#endif
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#ifdef CONFIG_SPIM1_RK29
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&rk29xx_device_spi1m,
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#endif
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#ifdef CONFIG_ADC_RK29
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@ -774,7 +776,7 @@ static struct spi_board_info board_spi_devices[] = {
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{
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.modalias = "xpt2046_ts",
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.chip_select = 0,
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.max_speed_hz = 125 * 1000 * 26,/* (max sample rate @ 3V) * (cmd + data + overhead) */
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.max_speed_hz = 125 * 1000 * 8,/* (max sample rate @ 3V) * (cmd + data + overhead) */
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.bus_num = 0,
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.irq = XPT2046_GPIO_INT,
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.platform_data = &xpt2046_info,
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@ -254,11 +254,23 @@ config SPIM_RK2818
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help
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general driver for SPI controller core from DesignWare
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config SPIM_RK29XX
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tristate "RK29xx SPI master controller core support"
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config SPIM_RK29
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tristate "RK29 SPI master controller core support"
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depends on ARCH_RK29 && SPI_MASTER
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help
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general driver for SPI controller core from DesignWare
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general driver for SPI controller core from RockChips
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config SPIM0_RK29
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bool "RK29 SPI0 master controller"
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depends on SPIM_RK29
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help
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enable SPI0 master controller for RK29
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config SPIM1_RK29
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bool "RK29 SPI1 master controller"
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depends on SPIM_RK29
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help
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enable SPI1 master controller for RK29
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#
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# There are lots of SPI device types, with sensors and memory
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@ -17,7 +17,7 @@ obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o
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obj-$(CONFIG_SPI_AU1550) += au1550_spi.o
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obj-$(CONFIG_SPI_BUTTERFLY) += spi_butterfly.o
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obj-$(CONFIG_SPIM_RK2818) += rk2818_spim.o
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obj-$(CONFIG_SPIM_RK29XX) += rk29xx_spim.o
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obj-$(CONFIG_SPIM_RK29) += rk29xx_spim.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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@ -40,8 +40,8 @@ QUICK_TRANSFER
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//#define QUICK_TRANSFER
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#if 0
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#define DBG(x...) printk(x)
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#if 1
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#define DBG printk
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#else
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#define DBG(x...)
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#endif
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@ -198,6 +198,7 @@ static void wait_till_not_busy(struct rk29xx_spi *dws)
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"DW SPI: Status keeps busy for 1000us after a read/write!\n");
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}
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#if defined(QUICK_TRANSFER)
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static void wait_till_tf_empty(struct rk29xx_spi *dws)
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{
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unsigned long end = jiffies + 1 + usecs_to_jiffies(1000);
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@ -209,6 +210,7 @@ static void wait_till_tf_empty(struct rk29xx_spi *dws)
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dev_err(&dws->master->dev,
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"DW SPI: Status keeps busy for 1000us after a read/write!\n");
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}
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#endif
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static void flush(struct rk29xx_spi *dws)
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{
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@ -238,7 +240,7 @@ static int null_writer(struct rk29xx_spi *dws)
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return 0;
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rk29xx_writew(dws, SPIM_TXDR, 0);
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dws->tx += n_bytes;
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wait_till_not_busy(dws);
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//wait_till_not_busy(dws);
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return 1;
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}
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@ -260,11 +262,9 @@ static int u8_writer(struct rk29xx_spi *dws)
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if ((rk29xx_readw(dws, SPIM_SR) & SR_TF_FULL)
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|| (dws->tx == dws->tx_end))
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return 0;
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DBG(KERN_INFO "ctrl0: 0x%x\n", rk29xx_readl(dws, SPIM_CTRLR0));
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rk29xx_writew(dws, SPIM_TXDR, *(u8 *)(dws->tx));
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DBG(KERN_INFO "dws->tx:%x\n", *(u8 *)(dws->tx));
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++dws->tx;
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wait_till_not_busy(dws);
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//wait_till_not_busy(dws);
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return 1;
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}
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@ -273,9 +273,7 @@ static int u8_reader(struct rk29xx_spi *dws)
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{
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while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)
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&& (dws->rx < dws->rx_end)) {
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printk(KERN_INFO "ctrl0: 0x%x\n", rk29xx_readl(dws, SPIM_CTRLR0));
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*(u8 *)(dws->rx) = rk29xx_readw(dws, SPIM_RXDR) & 0xFFU;
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printk(KERN_INFO "dws->rx:%x\n", *(u8 *)(dws->rx));
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++dws->rx;
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}
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@ -291,7 +289,7 @@ static int u16_writer(struct rk29xx_spi *dws)
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rk29xx_writew(dws, SPIM_TXDR, *(u16 *)(dws->tx));
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dws->tx += 2;
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wait_till_not_busy(dws);
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//wait_till_not_busy(dws);
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return 1;
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}
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@ -303,7 +301,6 @@ static int u16_reader(struct rk29xx_spi *dws)
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while (!(rk29xx_readw(dws, SPIM_SR) & SR_RF_EMPT)
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&& (dws->rx < dws->rx_end)) {
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temp = rk29xx_readw(dws, SPIM_RXDR);
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printk(KERN_INFO "dws->rx:%02x\n", temp);
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*(u16 *)(dws->rx) = temp;
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dws->rx += 2;
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}
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@ -328,7 +325,7 @@ static void *next_transfer(struct rk29xx_spi *dws)
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return DONE_STATE;
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}
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static void rk29_spi_dma_rxcb(struct rk29_dma_chan *chan, void *buf_id,
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static void rk29_spi_dma_rxcb(void *buf_id,
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int size, enum rk29_dma_buffresult res)
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{
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struct rk29xx_spi *dws = buf_id;
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@ -339,7 +336,7 @@ static void rk29_spi_dma_rxcb(struct rk29_dma_chan *chan, void *buf_id,
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if (res == RK29_RES_OK)
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dws->state &= ~RXBUSY;
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else
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dev_err(&dws->master->dev, "DmaAbrtRx-%d\n", size);
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dev_err(&dws->master->dev, "DmaAbrtRx-%d, size: %d\n", res, size);
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/* If the other done */
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if (!(dws->state & TXBUSY))
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@ -348,7 +345,7 @@ static void rk29_spi_dma_rxcb(struct rk29_dma_chan *chan, void *buf_id,
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spin_unlock_irqrestore(&dws->lock, flags);
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}
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static void rk29_spi_dma_txcb(struct rk29_dma_chan *chan, void *buf_id,
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static void rk29_spi_dma_txcb(void *buf_id,
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int size, enum rk29_dma_buffresult res)
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{
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struct rk29xx_spi *dws = buf_id;
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@ -362,7 +359,7 @@ static void rk29_spi_dma_txcb(struct rk29_dma_chan *chan, void *buf_id,
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dev_err(&dws->master->dev, "DmaAbrtTx-%d \n", size);
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/* If the other done */
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if (!(dws->state & RXBUSY))
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if (!(dws->state & RXBUSY))
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complete(&dws->xfer_completion);
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spin_unlock_irqrestore(&dws->lock, flags);
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@ -375,38 +372,33 @@ static struct rk29_dma_client rk29_spi_dma_client = {
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static int acquire_dma(struct rk29xx_spi *dws)
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{
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#if 1
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dws->dma_inited = 0;
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return 1;
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#endif
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if (dws->dma_inited) {
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return 1;
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return 0;
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}
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if(rk29_dma_request(dws->rx_dmach,
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&rk29_spi_dma_client, NULL) < 0) {
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dev_err(&dws->master->dev, "dws->rx_dmach : %d, cannot get RxDMA\n", dws->rx_dmach);
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return 0;
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return -1;
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}
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DBG(KERN_INFO "request dma success\n");
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rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb);
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rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,
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dws->sfr_start + SPIM_RXDR);
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if (rk29_dma_request(dws->tx_dmach,
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&rk29_spi_dma_client, NULL) < 0) {
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dev_err(&dws->master->dev, "dws->tx_dmach : %d, cannot get TxDMA\n", dws->tx_dmach);
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rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);
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return 0;
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return -1;
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}
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rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb);
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rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,
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dws->sfr_start + SPIM_TXDR);
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dws->dma_inited = 1;
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return 1;
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return 0;
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}
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static void release_dma(struct rk29xx_spi *dws)
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{
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if(!dws && dws->dma_inited) {
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rk29_dma_free(dws->rx_dmach, &rk29_spi_dma_client);
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rk29_dma_free(dws->tx_dmach, &rk29_spi_dma_client);
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}
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}
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/*
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@ -418,15 +410,35 @@ static int map_dma_buffers(struct rk29xx_spi *dws)
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{
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if (!dws->cur_msg->is_dma_mapped || !dws->dma_inited
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|| !dws->cur_chip->enable_dma)
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return 0;
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return -1;
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if (dws->cur_transfer->tx_dma)
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if (dws->cur_transfer->tx_dma) {
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dws->tx_dma = dws->cur_transfer->tx_dma;
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if (rk29_dma_set_buffdone_fn(dws->tx_dmach, rk29_spi_dma_txcb)) {
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dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");
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return -1;
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}
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if (rk29_dma_devconfig(dws->tx_dmach, RK29_DMASRC_MEM,
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(unsigned long)dws->sfr_start + SPIM_TXDR)) {
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dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");
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return -1;
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}
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}
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if (dws->cur_transfer->rx_dma)
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if (dws->cur_transfer->rx_dma) {
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dws->rx_dma = dws->cur_transfer->rx_dma;
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if (rk29_dma_set_buffdone_fn(dws->rx_dmach, rk29_spi_dma_rxcb)) {
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dev_err(&dws->master->dev, "rk29_dma_set_buffdone_fn fail\n");
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return -1;
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}
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if (rk29_dma_devconfig(dws->rx_dmach, RK29_DMASRC_HW,
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(unsigned long)dws->sfr_start + SPIM_RXDR)) {
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dev_err(&dws->master->dev, "rk29_dma_devconfig fail\n");
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return -1;
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}
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}
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return 1;
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return 0;
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}
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/* Caller already set message->status; dma and pio irqs are blocked */
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@ -451,7 +463,7 @@ static void giveback(struct rk29xx_spi *dws)
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transfer_list);
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if (!last_transfer->cs_change)
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dws->cs_control(dws,msg->spi->chip_select,MRST_SPI_DEASSERT);
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dws->cs_control(dws,msg->spi->chip_select, MRST_SPI_DEASSERT);
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msg->state = NULL;
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if (msg->complete)
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@ -537,45 +549,12 @@ static irqreturn_t rk29xx_spi_irq(int irq, void *dev_id)
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/* Must be called inside pump_transfers() */
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static void poll_transfer(struct rk29xx_spi *dws)
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{
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DBG(KERN_INFO "poll_transfer\n");
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while (dws->write(dws)) {
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wait_till_not_busy(dws);
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dws->read(dws);
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}
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transfer_complete(dws);
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}
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static void dma_transfer(struct rk29xx_spi *dws, struct spi_transfer *xfer) //int cs_change)
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{
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unsigned long val;
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int ms;
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DBG(KERN_INFO "dma_transfer\n");
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if (xfer->tx_buf != NULL) {
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dws->state |= TXBUSY;
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rk29_dma_config(dws->tx_dmach, 4);
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rk29_dma_enqueue(dws->tx_dmach, (void *)dws,
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xfer->tx_dma, xfer->len);
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rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START);
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}
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if (xfer->rx_buf != NULL) {
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dws->state |= RXBUSY;
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rk29_dma_config(dws->rx_dmach, 4);
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rk29_dma_enqueue(dws->rx_dmach, (void *)dws,
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xfer->rx_dma, xfer->len);
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rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START);
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}
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/* millisecs to xfer 'len' bytes @ 'cur_speed' */
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ms = xfer->len * 8 * 1000 / dws->cur_speed;
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ms += 10; /* some tolerance */
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val = msecs_to_jiffies(ms) + 10;
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val = wait_for_completion_timeout(&dws->xfer_completion, val);
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}
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static void spi_chip_sel(struct rk29xx_spi *dws, u16 cs)
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{
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if(cs >= dws->master->num_chipselect)
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@ -612,7 +591,8 @@ static void pump_transfers(unsigned long data)
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chip = dws->cur_chip;
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spi = message->spi;
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if (unlikely(!chip->clk_div))
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chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
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//chip->clk_div = clk_get_rate(dws->clock_spim) / chip->speed_hz;
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chip->clk_div = 40000000 / chip->speed_hz;
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if (message->state == ERROR_STATE) {
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message->status = -EIO;
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goto early_exit;
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@ -673,6 +653,7 @@ static void pump_transfers(unsigned long data)
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chip->clk_div = clk_div;
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}
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}
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if (transfer->bits_per_word) {
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bits = transfer->bits_per_word;
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@ -703,6 +684,8 @@ static void pump_transfers(unsigned long data)
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}
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cr0 = (spi_dfs << SPI_DFS_OFFSET)
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| (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
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| (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
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| (chip->type << SPI_FRF_OFFSET)
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| (spi->mode << SPI_MODE_OFFSET)
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| (chip->tmode << SPI_TMOD_OFFSET);
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@ -723,9 +706,7 @@ static void pump_transfers(unsigned long data)
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cr0 &= ~(0x3 << SPI_MODE_OFFSET);
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cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
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}
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/* Check if current transfer is a DMA transaction */
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dws->dma_mapped = map_dma_buffers(dws);
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}
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/*
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* Interrupt mode
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@ -760,13 +741,11 @@ static void pump_transfers(unsigned long data)
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if (txint_level)
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rk29xx_writew(dws, SPIM_TXFTLR, txint_level);
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rk29xx_writew(dws, SPIM_CTRLR1, dws->len-1);
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spi_enable_chip(dws, 1);
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if (cs_change)
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dws->prev_chip = chip;
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}
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if (dws->dma_mapped && transfer->len > DMA_MIN_BYTES)
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dma_transfer(dws, transfer); ///cs_change);
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}
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if (chip->poll_mode)
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poll_transfer(dws);
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@ -778,6 +757,269 @@ static void pump_transfers(unsigned long data)
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return;
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}
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static void dma_transfer(struct rk29xx_spi *dws) //int cs_change)
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{
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struct spi_message *message = NULL;
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struct spi_transfer *transfer = NULL;
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struct spi_transfer *previous = NULL;
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struct spi_device *spi = NULL;
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struct chip_data *chip = NULL;
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unsigned long val;
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int ms;
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int iRet;
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u8 bits = 0;
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u8 spi_dfs = 0;
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u8 cs_change = 0;
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u16 clk_div = 0;
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u32 speed = 0;
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u32 cr0 = 0;
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u32 dmacr = 0;
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DBG(KERN_INFO "dma_transfer\n");
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if (acquire_dma(dws)) {
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dev_err(&dws->master->dev, "acquire dma failed\n");
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goto err_out;
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}
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if (map_dma_buffers(dws)) {
|
||||
dev_err(&dws->master->dev, "acquire dma failed\n");
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
/* Get current state information */
|
||||
message = dws->cur_msg;
|
||||
transfer = dws->cur_transfer;
|
||||
chip = dws->cur_chip;
|
||||
spi = message->spi;
|
||||
if (unlikely(!chip->clk_div))
|
||||
chip->clk_div = 40000000 / chip->speed_hz;
|
||||
if (message->state == ERROR_STATE) {
|
||||
message->status = -EIO;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
/* Handle end of message */
|
||||
if (message->state == DONE_STATE) {
|
||||
message->status = 0;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
/* Delay if requested at end of transfer*/
|
||||
if (message->state == RUNNING_STATE) {
|
||||
previous = list_entry(transfer->transfer_list.prev,
|
||||
struct spi_transfer,
|
||||
transfer_list);
|
||||
if (previous->delay_usecs)
|
||||
udelay(previous->delay_usecs);
|
||||
}
|
||||
|
||||
dws->n_bytes = chip->n_bytes;
|
||||
dws->dma_width = chip->dma_width;
|
||||
dws->cs_control = chip->cs_control;
|
||||
|
||||
dws->rx_dma = transfer->rx_dma;
|
||||
dws->tx_dma = transfer->tx_dma;
|
||||
dws->tx = (void *)transfer->tx_buf;
|
||||
dws->tx_end = dws->tx + transfer->len;
|
||||
dws->rx = transfer->rx_buf;
|
||||
dws->rx_end = dws->rx + transfer->len;
|
||||
dws->write = dws->tx ? chip->write : null_writer;
|
||||
dws->read = dws->rx ? chip->read : null_reader;
|
||||
dws->cs_change = transfer->cs_change;
|
||||
dws->len = dws->cur_transfer->len;
|
||||
if (chip != dws->prev_chip)
|
||||
cs_change = 1;
|
||||
|
||||
cr0 = chip->cr0;
|
||||
|
||||
/* Handle per transfer options for bpw and speed */
|
||||
if (transfer->speed_hz) {
|
||||
speed = chip->speed_hz;
|
||||
|
||||
if (transfer->speed_hz != speed) {
|
||||
speed = transfer->speed_hz;
|
||||
if (speed > clk_get_rate(dws->clock_spim)) {
|
||||
dev_err(&dws->master->dev, "MRST SPI0: unsupported"
|
||||
"freq: %dHz\n", speed);
|
||||
message->status = -EIO;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
/* clk_div doesn't support odd number */
|
||||
clk_div = clk_get_rate(dws->clock_spim) / speed;
|
||||
clk_div = (clk_div + 1) & 0xfffe;
|
||||
|
||||
chip->speed_hz = speed;
|
||||
chip->clk_div = clk_div;
|
||||
}
|
||||
}
|
||||
|
||||
if (transfer->bits_per_word) {
|
||||
bits = transfer->bits_per_word;
|
||||
|
||||
switch (bits) {
|
||||
case 8:
|
||||
dws->n_bytes = 1;
|
||||
dws->dma_width = 1;
|
||||
spi_dfs = SPI_DFS_8BIT;
|
||||
break;
|
||||
case 16:
|
||||
dws->n_bytes = 2;
|
||||
dws->dma_width = 2;
|
||||
spi_dfs = SPI_DFS_16BIT;
|
||||
break;
|
||||
default:
|
||||
dev_err(&dws->master->dev, "MRST SPI0: unsupported bits:"
|
||||
"%db\n", bits);
|
||||
message->status = -EIO;
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
cr0 = (spi_dfs << SPI_DFS_OFFSET)
|
||||
| (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
|
||||
| (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
|
||||
| (chip->type << SPI_FRF_OFFSET)
|
||||
| (spi->mode << SPI_MODE_OFFSET)
|
||||
| (chip->tmode << SPI_TMOD_OFFSET);
|
||||
}
|
||||
message->state = RUNNING_STATE;
|
||||
|
||||
/*
|
||||
* Adjust transfer mode if necessary. Requires platform dependent
|
||||
* chipselect mechanism.
|
||||
*/
|
||||
if (dws->cs_control) {
|
||||
if (dws->rx && dws->tx)
|
||||
chip->tmode = SPI_TMOD_TR;
|
||||
else if (dws->rx)
|
||||
chip->tmode = SPI_TMOD_RO;
|
||||
else
|
||||
chip->tmode = SPI_TMOD_TO;
|
||||
|
||||
cr0 &= ~(0x3 << SPI_MODE_OFFSET);
|
||||
cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reprogram registers only if
|
||||
* 1. chip select changes
|
||||
* 2. clk_div is changed
|
||||
* 3. control value changes
|
||||
*/
|
||||
if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0 || cs_change || clk_div) {
|
||||
spi_enable_chip(dws, 0);
|
||||
if (rk29xx_readw(dws, SPIM_CTRLR0) != cr0) {
|
||||
rk29xx_writew(dws, SPIM_CTRLR0, cr0);
|
||||
}
|
||||
|
||||
spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
|
||||
spi_chip_sel(dws, spi->chip_select);
|
||||
/* Set the interrupt mask, for poll mode just diable all int */
|
||||
spi_mask_intr(dws, 0xff);
|
||||
|
||||
if (transfer->tx_buf != NULL) {
|
||||
dmacr |= SPI_DMACR_TX_ENABLE;
|
||||
rk29xx_writew(dws, SPIM_DMATDLR, 0);
|
||||
}
|
||||
if (transfer->rx_buf != NULL) {
|
||||
dmacr |= SPI_DMACR_RX_ENABLE;
|
||||
rk29xx_writew(dws, SPIM_DMARDLR, 0);
|
||||
rk29xx_writew(dws, SPIM_CTRLR1, transfer->len-1);
|
||||
}
|
||||
rk29xx_writew(dws, SPIM_DMACR, dmacr);
|
||||
spi_enable_chip(dws, 1);
|
||||
if (cs_change)
|
||||
dws->prev_chip = chip;
|
||||
}
|
||||
|
||||
INIT_COMPLETION(dws->xfer_completion);
|
||||
|
||||
if (transfer->tx_buf != NULL) {
|
||||
dws->state |= TXBUSY;
|
||||
if (rk29_dma_config(dws->tx_dmach, 1)) {
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
iRet = rk29_dma_enqueue(dws->tx_dmach, (void *)dws,
|
||||
transfer->tx_dma, transfer->len);
|
||||
if (iRet) {
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d, iRet: %d(dws->tx_dmach: %d, transfer->tx_dma: 0x%x)\n", __FUNCTION__, __LINE__, iRet,
|
||||
dws->tx_dmach, (unsigned int)transfer->tx_dma);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
if (rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_START)) {
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto err_out;
|
||||
}
|
||||
}
|
||||
|
||||
if (transfer->rx_buf != NULL) {
|
||||
dws->state |= RXBUSY;
|
||||
if (rk29_dma_config(dws->rx_dmach, 1)) {
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
iRet = rk29_dma_enqueue(dws->rx_dmach, (void *)dws,
|
||||
transfer->rx_dma, transfer->len);
|
||||
if (iRet) {
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
if (rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_START)) {
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto err_out;
|
||||
}
|
||||
}
|
||||
|
||||
/* millisecs to xfer 'len' bytes @ 'cur_speed' */
|
||||
ms = transfer->len * 8 * 1000 / dws->cur_chip->speed_hz;
|
||||
ms += 10;
|
||||
|
||||
val = msecs_to_jiffies(ms) + 500;
|
||||
if (!wait_for_completion_timeout(&dws->xfer_completion, val)) {
|
||||
if (transfer->rx_buf != NULL && (dws->state & RXBUSY)) {
|
||||
rk29_dma_ctrl(dws->rx_dmach, RK29_DMAOP_FLUSH);
|
||||
dws->state &= ~RXBUSY;
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto NEXT_TRANSFER;
|
||||
}
|
||||
if (transfer->tx_buf != NULL && (dws->state & TXBUSY)) {
|
||||
rk29_dma_ctrl(dws->tx_dmach, RK29_DMAOP_FLUSH);
|
||||
dws->state &= ~TXBUSY;
|
||||
dev_err(&dws->master->dev, "function: %s, line: %d\n", __FUNCTION__, __LINE__);
|
||||
goto NEXT_TRANSFER;
|
||||
}
|
||||
}
|
||||
|
||||
wait_till_not_busy(dws);
|
||||
|
||||
NEXT_TRANSFER:
|
||||
/* Update total byte transfered return count actual bytes read */
|
||||
dws->cur_msg->actual_length += dws->len;
|
||||
|
||||
/* Move to next transfer */
|
||||
dws->cur_msg->state = next_transfer(dws);
|
||||
|
||||
/* Handle end of message */
|
||||
if (dws->cur_msg->state == DONE_STATE) {
|
||||
dws->cur_msg->status = 0;
|
||||
giveback(dws);
|
||||
} else
|
||||
dma_transfer(dws);
|
||||
|
||||
return;
|
||||
|
||||
err_out:
|
||||
giveback(dws);
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
static void pump_messages(struct work_struct *work)
|
||||
{
|
||||
struct rk29xx_spi *dws =
|
||||
|
|
@ -786,9 +1028,6 @@ static void pump_messages(struct work_struct *work)
|
|||
|
||||
DBG(KERN_INFO "pump_messages\n");
|
||||
|
||||
while (!acquire_dma(dws))
|
||||
msleep(10);
|
||||
|
||||
/* Lock queue and check for queue work */
|
||||
spin_lock_irqsave(&dws->lock, flags);
|
||||
if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
|
||||
|
|
@ -816,7 +1055,15 @@ static void pump_messages(struct work_struct *work)
|
|||
dws->prev_chip = NULL; //ÿ¸öpump messageʱǿÖƸüÐÂcs dxj
|
||||
|
||||
/* Mark as busy and launch transfers */
|
||||
tasklet_schedule(&dws->pump_transfers);
|
||||
if(dws->cur_msg->is_dma_mapped && dws->cur_transfer->len > DMA_MIN_BYTES) {
|
||||
dws->busy = 1;
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
dma_transfer(dws);
|
||||
return;
|
||||
}
|
||||
else {
|
||||
tasklet_schedule(&dws->pump_transfers);
|
||||
}
|
||||
|
||||
dws->busy = 1;
|
||||
spin_unlock_irqrestore(&dws->lock, flags);
|
||||
|
|
@ -1116,15 +1363,10 @@ static int rk29xx_pump_transfers(struct rk29xx_spi *dws, int mode)
|
|||
if (cs_change)
|
||||
dws->prev_chip = chip;
|
||||
|
||||
if (dws->dma_mapped && transfer->len > DMA_MIN_BYTES) {
|
||||
dma_transfer(dws, transfer);
|
||||
}
|
||||
else {
|
||||
if (mode)
|
||||
return do_full_transfer(dws);
|
||||
else
|
||||
return do_half_transfer(dws);
|
||||
}
|
||||
if (mode)
|
||||
return do_full_transfer(dws);
|
||||
else
|
||||
return do_half_transfer(dws);
|
||||
|
||||
early_exit:
|
||||
|
||||
|
|
@ -1319,6 +1561,8 @@ static int rk29xx_spi_setup(struct spi_device *spi)
|
|||
chip->tmode = 0; /* Tx & Rx */
|
||||
/* Default SPI mode is SCPOL = 0, SCPH = 0 */
|
||||
chip->cr0 = (spi_dfs << SPI_DFS_OFFSET)
|
||||
| (SPI_HALF_WORLD_OFF << SPI_HALF_WORLD_TX_OFFSET)
|
||||
| (SPI_SSN_DELAY_ONE << SPI_SSN_DELAY_OFFSET)
|
||||
| (chip->type << SPI_FRF_OFFSET)
|
||||
| (spi->mode << SPI_MODE_OFFSET)
|
||||
| (chip->tmode << SPI_TMOD_OFFSET);
|
||||
|
|
@ -1341,6 +1585,8 @@ static int __devinit init_queue(struct rk29xx_spi *dws)
|
|||
dws->run = QUEUE_STOPPED;
|
||||
dws->busy = 0;
|
||||
|
||||
init_completion(&dws->xfer_completion);
|
||||
|
||||
tasklet_init(&dws->pump_transfers,
|
||||
pump_transfers, (unsigned long)dws);
|
||||
|
||||
|
|
@ -1582,7 +1828,7 @@ static int __init rk29xx_spim_probe(struct platform_device *pdev)
|
|||
|
||||
ret =rk29xx_spim_cpufreq_register(dws);
|
||||
if (ret < 0) {
|
||||
printk(KERN_ERR"rk29xx spim failed to init cpufreq support\n");
|
||||
dev_err(&master->dev, "rk29xx spim failed to init cpufreq support\n");
|
||||
goto err_queue_alloc;
|
||||
}
|
||||
DBG(KERN_INFO "rk29xx_spim: driver initialized\n");
|
||||
|
|
@ -1612,6 +1858,8 @@ static void __exit rk29xx_spim_remove(struct platform_device *pdev)
|
|||
rk29xx_spim_cpufreq_deregister(dws);
|
||||
mrst_spi_debugfs_remove(dws);
|
||||
|
||||
release_dma(dws);
|
||||
|
||||
/* Remove the queue */
|
||||
status = destroy_queue(dws);
|
||||
if (status != 0)
|
||||
|
|
|
|||
|
|
@ -73,6 +73,14 @@
|
|||
#define SPI_CSM_HALF 0x01 /* ss_n be high for half sclk_out cycles after every frame data is transferred */
|
||||
#define SPI_CSM_ONE 0x02 /* ss_n be high for one sclk_out cycle after every frame data is transferred */
|
||||
|
||||
#define SPI_SSN_DELAY_OFFSET 10
|
||||
#define SPI_SSN_DELAY_HALF 0x00
|
||||
#define SPI_SSN_DELAY_ONE 0x01
|
||||
|
||||
#define SPI_HALF_WORLD_TX_OFFSET 13
|
||||
#define SPI_HALF_WORLD_ON 0x00
|
||||
#define SPI_HALF_WORLD_OFF 0x01
|
||||
|
||||
|
||||
/* --------Bit fields in CTRLR0--------end */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user