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drm/amdgpu: Correct inst_id input from physical to logic
Correct inst_id input from physical to logic for sdma v7_1. V2: Show real instance number on logic xcc. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1eb2a5ed19
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@ -369,7 +369,7 @@ static void sdma_v7_1_inst_gfx_stop(struct amdgpu_device *adev,
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u32 rb_cntl, ib_cntl;
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int i;
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for_each_inst(i, inst_mask) {
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for (i = 0; i < NUM_XCC(inst_mask); i++) {
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rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL));
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rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 0);
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WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl);
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@ -436,7 +436,7 @@ static void sdma_v7_1_inst_enable(struct amdgpu_device *adev,
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if (amdgpu_sriov_vf(adev))
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return;
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for_each_inst(i, inst_mask) {
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for (i = 0; i < NUM_XCC(inst_mask); i++) {
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mcu_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL));
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mcu_cntl = REG_SET_FIELD(mcu_cntl, SDMA0_SDMA_MCU_CNTL, HALT, enable ? 0 : 1);
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WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_MCU_CNTL), mcu_cntl);
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@ -617,7 +617,7 @@ static int sdma_v7_1_inst_gfx_resume(struct amdgpu_device *adev,
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{
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int i, r;
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for_each_inst(i, inst_mask) {
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for (i = 0; i < NUM_XCC(inst_mask); i++) {
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r = sdma_v7_1_gfx_resume_instance(adev, i, false);
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if (r)
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return r;
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@ -647,7 +647,7 @@ static void sdma_v7_1_inst_free_ucode_buffer(struct amdgpu_device *adev,
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{
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int i;
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for_each_inst(i, inst_mask) {
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for (i = 0; i < NUM_XCC(inst_mask); i++) {
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amdgpu_bo_free_kernel(&adev->sdma.instance[i].sdma_fw_obj,
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&adev->sdma.instance[i].sdma_fw_gpu_addr,
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(void **)&adev->sdma.instance[i].sdma_fw_ptr);
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@ -686,7 +686,7 @@ static int sdma_v7_1_inst_load_microcode(struct amdgpu_device *adev,
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le32_to_cpu(hdr->ucode_offset_bytes));
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fw_size = le32_to_cpu(hdr->ucode_size_bytes);
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for_each_inst(i, inst_mask) {
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for (i = 0; i < NUM_XCC(inst_mask); i++) {
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r = amdgpu_bo_create_reserved(adev, fw_size,
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PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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@ -744,10 +744,10 @@ static int sdma_v7_1_soft_reset(struct amdgpu_ip_block *ip_block)
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u32 tmp;
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int i;
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inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
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inst_mask = adev->sdma.sdma_mask;
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sdma_v7_1_inst_gfx_stop(adev, inst_mask);
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for_each_inst(i, inst_mask) {
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for (i = 0; i < NUM_XCC(inst_mask); i++) {
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//tmp = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FREEZE));
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//tmp |= SDMA0_SDMA_FREEZE__FREEZE_MASK;
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//WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_FREEZE), tmp);
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@ -1288,10 +1288,14 @@ static int sdma_v7_1_sw_init(struct amdgpu_ip_block *ip_block)
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ring->ring_obj = NULL;
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ring->use_doorbell = true;
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ring->me = i;
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xcc_id = adev->sdma.instance[i].xcc_id;
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for (xcc_id = 0; xcc_id < fls(adev->gfx.xcc_mask); xcc_id++) {
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if (adev->sdma.instance[i].xcc_id == GET_INST(GC, xcc_id))
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break;
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}
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DRM_DEBUG("SDMA%d.%d use_doorbell being set to: [%s]\n",
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xcc_id, i % adev->sdma.num_inst_per_xcc,
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xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc,
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ring->use_doorbell?"true":"false");
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ring->doorbell_index =
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@ -1299,7 +1303,7 @@ static int sdma_v7_1_sw_init(struct amdgpu_ip_block *ip_block)
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ring->vm_hub = AMDGPU_GFXHUB(xcc_id);
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sprintf(ring->name, "sdma%d.%d", xcc_id,
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i % adev->sdma.num_inst_per_xcc);
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GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc);
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r = amdgpu_ring_init(adev, ring, 1024,
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&adev->sdma.trap_irq,
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AMDGPU_SDMA_IRQ_INSTANCE0 + i,
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@ -1334,11 +1338,8 @@ static int sdma_v7_1_sw_init(struct amdgpu_ip_block *ip_block)
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static int sdma_v7_1_sw_fini(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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uint32_t inst_mask;
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int i;
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inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
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for (i = 0; i < adev->sdma.num_instances; i++)
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amdgpu_ring_fini(&adev->sdma.instance[i].ring);
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@ -1346,7 +1347,7 @@ static int sdma_v7_1_sw_fini(struct amdgpu_ip_block *ip_block)
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amdgpu_sdma_destroy_inst_ctx(adev, true);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)
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sdma_v7_1_inst_free_ucode_buffer(adev, inst_mask);
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sdma_v7_1_inst_free_ucode_buffer(adev, adev->sdma.sdma_mask);
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kfree(adev->sdma.ip_dump);
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@ -1356,24 +1357,19 @@ static int sdma_v7_1_sw_fini(struct amdgpu_ip_block *ip_block)
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static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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uint32_t inst_mask;
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inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
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return sdma_v7_1_inst_start(adev, inst_mask);
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return sdma_v7_1_inst_start(adev, adev->sdma.sdma_mask);
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}
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static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block)
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{
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struct amdgpu_device *adev = ip_block->adev;
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uint32_t inst_mask;
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if (amdgpu_sriov_vf(adev))
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return 0;
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inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
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sdma_v7_1_inst_ctx_switch_enable(adev, false, inst_mask);
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sdma_v7_1_inst_enable(adev, false, inst_mask);
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sdma_v7_1_inst_ctx_switch_enable(adev, false, adev->sdma.sdma_mask);
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sdma_v7_1_inst_enable(adev, false, adev->sdma.sdma_mask);
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return 0;
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}
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@ -1493,7 +1489,7 @@ static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev,
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struct amdgpu_irq_src *source,
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struct amdgpu_iv_entry *entry)
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{
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int instances, queue, xcc_id = 0;
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int inst, instances, queue, xcc_id = 0;
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uint32_t mes_queue_id = entry->src_data[0];
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DRM_DEBUG("IH: SDMA trap\n");
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@ -1518,8 +1514,12 @@ static int sdma_v7_1_process_trap_irq(struct amdgpu_device *adev,
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xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev, entry->node_id);
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else
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dev_warn(adev->dev, "IH: SDMA may get wrong xcc id as gfx function not available\n");
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instances = ((entry->ring_id & 0xf0) >> 4) +
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xcc_id * adev->sdma.num_inst_per_xcc;
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inst = ((entry->ring_id & 0xf0) >> 4) +
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GET_INST(GC, xcc_id) * adev->sdma.num_inst_per_xcc;
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for (instances = 0; instances < adev->sdma.num_instances; instances++) {
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if (inst == GET_INST(SDMA0, instances))
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break;
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}
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if (instances > adev->sdma.num_instances - 1) {
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DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
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return -EINVAL;
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