From 49dda19957e855d4849bbbf305eb25ca4116b539 Mon Sep 17 00:00:00 2001 From: Finley Xiao Date: Thu, 7 Dec 2017 20:29:25 +0800 Subject: [PATCH] arm: dts: rockchip: Add clock assign for rk3126 and rk3128 cru Add "assigned-clocks" for rk3126 and rk3128 cru nodes, to intalize clock rate for plls, bus and peripher. Change-Id: Ie91c8b194feff5db91af6e9930d5f475175242f9 Signed-off-by: Finley Xiao --- arch/arm/boot/dts/rk3126.dtsi | 12 ++++-------- arch/arm/boot/dts/rk3128.dtsi | 8 -------- arch/arm/boot/dts/rk312x.dtsi | 16 ++++++++++++++++ 3 files changed, 20 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/rk3126.dtsi b/arch/arm/boot/dts/rk3126.dtsi index 379cf2649e78..e386490097bb 100644 --- a/arch/arm/boot/dts/rk3126.dtsi +++ b/arch/arm/boot/dts/rk3126.dtsi @@ -42,12 +42,8 @@ / { compatible = "rockchip,rk3126"; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3126-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; +}; + +&cru { + compatible = "rockchip,rk3126-cru"; }; diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rk3128.dtsi index 977cf008d543..b3cb21a281fc 100644 --- a/arch/arm/boot/dts/rk3128.dtsi +++ b/arch/arm/boot/dts/rk3128.dtsi @@ -47,14 +47,6 @@ qos_ebc: qos@1012f080 { compatible = "syscon"; reg = <0x1012f080 0x20>; }; - - cru: clock-controller@20000000 { - compatible = "rockchip,rk3128-cru"; - reg = <0x20000000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - }; }; &pd_vio { diff --git a/arch/arm/boot/dts/rk312x.dtsi b/arch/arm/boot/dts/rk312x.dtsi index 6d73ca6a4f80..864cc2dfbb34 100644 --- a/arch/arm/boot/dts/rk312x.dtsi +++ b/arch/arm/boot/dts/rk312x.dtsi @@ -743,6 +743,22 @@ nandc: nandc@10500000 { status = "disabled"; }; + cru: clock-controller@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru ACLK_CPU>, <&cru HCLK_CPU>, + <&cru PCLK_CPU>, <&cru ACLK_PERI>, + <&cru HCLK_PERI>, <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <300000000>, <150000000>, + <75000000>, <300000000>, + <150000000>, <75000000>; + }; + grf: syscon@20008000 { compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>;