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Linux 7.3-rc1

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Merge tag 'v7.3-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into gpio/for-current

Linux 7.3-rc1
This commit is contained in:
Bartosz Golaszewski 2026-09-01 09:16:55 +02:00
commit 49bda48268
1352 changed files with 54032 additions and 13861 deletions
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7
.mailmap
View File

@ -242,6 +242,10 @@ Daniele Alessandrelli <daniele.alessandrelli@gmail.com> <daniele.alessandrelli@i
Danila Tikhonov <danila@mainlining.org> <danila@jiaxyga.com>
Danila Tikhonov <danila@mainlining.org> <JIaxyga@protonmail.com>
Danilo Krummrich <dakr@kernel.org> <dakr@redhat.com>
Darrick J. Wong <djwong@kernel.org> <djwong@us.ibm.com>
Darrick J. Wong <djwong@kernel.org> <darrick.wong@oracle.com>
Darrick J. Wong <djwong@kernel.org> <djwong@flax.djwong.org>
Darrick J. Wong <djwong@kernel.org> <djwong@djwong.org>
David Brownell <david-b@pacbell.net>
David Collins <quic_collinsd@quicinc.com> <collinsd@codeaurora.org>
David Gow <david@davidgow.net> <davidgow@google.com>
@ -577,6 +581,9 @@ Mark Brown <broonie@sirena.org.uk>
Mark Starovoytov <mstarovo@pm.me> <mstarovoitov@marvell.com>
Markus Schneider-Pargmann <msp@baylibre.com> <mpa@pengutronix.de>
Mark Yao <markyao0591@gmail.com> <mark.yao@rock-chips.com>
Martin K. Petersen <mkp@kernel.org> <martin.petersen@oracle.com>
Martin K. Petersen <mkp@kernel.org> <mkp@mkp.net>
Martin K. Petersen <mkp@kernel.org> <mkp@linuxcare.com>
Martin Kepplinger-Novakovic <martink@posteo.de> <martin.kepplinger-novakovic@ginzinger.com>
Martyna Szapar-Mudlaw <martyna.szapar-mudlaw@linux.intel.com> <martyna.szapar-mudlaw@intel.com>
Mathieu Othacehe <othacehe@gnu.org> <m.othacehe@gmail.com>

15
CREDITS
View File

@ -2919,6 +2919,10 @@ N: Thomas Molina
E: tmolina@cablespeed.com
D: bug fixes, documentation, minor hackery
N: Bob Moore
E: robert.moore@intel.com
D: ACPI Component Architecture (ACPICA)
N: Paul Moore
E: paul@paul-moore.com
W: https://www.paul-moore.com
@ -4112,6 +4116,10 @@ S: 4226 Landgreen Street
S: Rockville, Maryland 20853
S: USA
N: Michael Turquette
E: mturquette@baylibre.com
D: common clk maintenance
N: Stephen Tweedie
E: sct@redhat.com
P: 1024/E7A417AD E2 FE A4 20 34 EC ED FC 7D 7E 67 8D E0 31 D1 69
@ -4461,6 +4469,13 @@ S: The Netherlands
N: Thomas Woller
D: CS461x Cirrus Logic sound driver
N: Darrick J. Wong
E: djwong@kernel.org
D: ext4 filesystem
D: XFS filesystem and online fsck
D: Various hwmon drivers
S: USA
N: David Woodhouse
E: dwmw2@infradead.org
D: JFFS2 file system, Memory Technology Device subsystem,

18
Documentation/ABI/testing/sysfs-fs-f2fs
View File

@ -986,6 +986,7 @@ Description: This sysfs entry can be used to enable/disable to adjust priority f
0x00000008 gc_lock
0x00000010 cp_global
0x00000020 io_rwsem
0x00000040 nat_tree_lock
========== ==================
What: /sys/fs/f2fs/<disk>/lock_duration_priority
@ -1002,3 +1003,20 @@ Description: It can be used to tune priority of f2fs critical task, e.g. f2fs_ck
threads, limitation as below:
- it requires user has CAP_SYS_NICE capability.
- the range is [100, 139], by default the value is 120.
What: /sys/fs/f2fs/<disk>/max_atc_write_bio_size
Date: June 2026
Contact: Bart Van Assche <bvanassche@acm.org>
Description: Every time a write operation completes f2fs_write_end_io() is
called. This function may be called from an atomic context,
e.g. from inside an interrupt handler. This attribute controls
the maximum size of a write bio that is completed in atomic
(atc) context. The default value for this attribute is UINT_MAX
which means that this functionality is disabled by default.
What: /sys/fs/f2fs/<disk>/pinned_area_max_secno
Date: August 2026
Contact: "Daeho Jeong" <daehojeong@google.com>
Description: This is a read-only entry to show the upper bound section number
for pinned files. Pinned files will only be allocated within
sections 0 to pinned_area_max_secno - 1.

40
Documentation/admin-guide/blockdev/zram.rst
View File

@ -109,14 +109,41 @@ path to the `dict` along with other parameters::
#pass path to pre-trained zstd dictionary
echo "algo=zstd dict=/etc/dictionary" > /sys/block/zram0/algorithm_params
#same, but using algorithm priority
echo "priority=1 dict=/etc/dictionary" > \
/sys/block/zram0/algorithm_params
#pass path to pre-trained zstd dictionary and compression level
echo "algo=zstd level=8 dict=/etc/dictionary" > \
/sys/block/zram0/algorithm_params
#same, but using algorithm priority
echo "algo=zstd priority=1" > /sys/block/zram0/recomp_algorithm
echo "priority=1 dict=/etc/dictionary" > \
/sys/block/zram0/algorithm_params
Each write to `algorithm_params` replaces the entire set of parameters of
the corresponding algorithm, parameters that are not listed in the write
are reset to their default values. Configure all of the parameters of an
algorithm in one write::
#WRONG: the second write resets level back to its default value
echo "algo=zstd level=8" > /sys/block/zram0/algorithm_params
echo "algo=zstd dict=/etc/dictionary" > /sys/block/zram0/algorithm_params
#RIGHT
echo "algo=zstd level=8 dict=/etc/dictionary" > \
/sys/block/zram0/algorithm_params
Select the compression algorithm before configuring its parameters. The
parameters of one algorithm are not necessarily valid for another one, so
changing the algorithm of a particular priority resets that priority's
parameters::
#WRONG: comp_algorithm write resets the previously configured level
echo "level=8" > /sys/block/zram0/algorithm_params
echo zstd > /sys/block/zram0/comp_algorithm
#RIGHT
echo zstd > /sys/block/zram0/comp_algorithm
echo "algo=zstd level=8" > /sys/block/zram0/algorithm_params
Parameters are algorithm specific: not all algorithms support pre-trained
dictionaries, not all algorithms support `level`. Furthermore, for certain
algorithms `level` controls the compression level (the higher the value the
@ -124,6 +151,11 @@ better the compression ratio, it even can take negatives values for some
algorithms), for other algorithms `level` is acceleration level (the higher
the value the lower the compression ratio).
Parameters are handed over to the compression algorithm when the device is
initialised, hence invalid parameters (or parameters that the selected
algorithm does not support) are reported by the `disksize` write, and not
by the `algorithm_params` write that has configured them.
Set Disksize
============

37
Documentation/admin-guide/kernel-parameters.txt
View File

@ -8,6 +8,8 @@
ARM64 ARM64 architecture is enabled.
CLK Common clock infrastructure is enabled.
CMA Contiguous Memory Area support is enabled.
CPU_FREQ CPU frequency scaling is enabled.
CPU_IDLE CPU idle time management is enabled.
DRM Direct Rendering Management support is enabled.
DYNAMIC_DEBUG Build in debug messages and enable them at runtime
EARLY Parameter processed too early to be embedded in initrd.
@ -2075,8 +2077,14 @@ Kernel parameters
hugetlb_cma= [HW,CMA,EARLY] The size of a CMA area used for allocation
of gigantic hugepages. Or using node format, the size
of a CMA area per node can be specified.
Format: nn[KMGTPE] or (node format)
<node>:nn[KMGTPE][,<node>:nn[KMGTPE]]
The size can be an absolute value (e.g., 2G) or a
percentage of the total memory or node memory (e.g., 20%).
Percentage-derived sizes are rounded down to a multiple of
the architecture's gigantic hugepage size and may become
zero.
Format: nn[KMGTPE] or nn% or (node format)
<node>:nn[KMGTPE][,<node>:nn[KMGTPE]] or
<node>:nn%[,<node>:nn%]
The size must be a multiple of the gigantic page size.
When using node format, this applies to each per-node size.
@ -4852,6 +4860,12 @@ Kernel parameters
Adjust the minimal page reporting order. The page
reporting is disabled when it exceeds MAX_PAGE_ORDER.
page_reporting.page_reporting_delay_ms=
[KNL] Free page reporting delay in milliseconds
Format: <unsigned integer>
Adjust the delay in milliseconds between free page
reporting intervals. Default is 2000 (2 seconds).
panic= [KNL] Kernel behaviour on panic: delay <timeout>
timeout > 0: seconds before rebooting
timeout = 0: wait forever
@ -4892,6 +4906,7 @@ Kernel parameters
panic_print= Bitmask for printing system info when panic happens.
User can chose combination of the following bits:
bit 0: print all tasks info
bit 1: print system memory info
bit 2: print timer info
@ -4900,10 +4915,16 @@ Kernel parameters
bit 5: replay all kernel messages on consoles at the end of panic
bit 6: print all CPUs backtrace (if available in the arch)
bit 7: print only tasks in uninterruptible (blocked) state
*Be aware* that this option may print a _lot_ of lines,
so there are risks of losing older messages in the log.
Use this option carefully, maybe worth to setup a
bigger log buffer with "log_buf_len" along with this.
*Be aware* that this option may print a _lot_ of lines.
There is an increased risk of losing older messages in
the log. Maybe worth to setup a bigger log buffer with
"log_buf_len" along with this.
Also consider using "printk.console_no_auto_verbose=Y"
if using this along with pstore, to avoid extra delays
due to increased console verbosity during panic.
panic_sys_info= A comma separated list of extra information to be dumped
on panic.
@ -4918,7 +4939,9 @@ Kernel parameters
all_bt: print all CPUs backtrace (if available in the arch)
blocked_tasks: print only tasks in uninterruptible (blocked) state
This is a human readable alternative to the 'panic_print' option.
This is a human readable alternative to the 'panic_print'
option above. Please be aware of the caveats using this,
check the 'panic_print' parameter for more details.
panic_console_replay
When panic happens, replay all kernel messages on

6
Documentation/admin-guide/mm/transhuge.rst
View File

@ -224,7 +224,7 @@ khugepaged will be automatically started when any THP size is enabled
(either of the per-size anon control or the top-level control are set
to "always" or "madvise"), and it'll be automatically shutdown when
all THP sizes are disabled (when both the per-size anon control and the
top-level control are "never")
top-level control are "never").
process THP controls
--------------------
@ -301,7 +301,9 @@ being replaced by a PMD mapping, or (2) physical pages replaced by one
hugepage of various sizes (PMD-sized or mTHP). Each may happen independently,
or together, depending on the type of memory and the failures that occur.
As such, this value should be interpreted roughly as a sign of progress,
and counters in /proc/vmstat consulted for more accurate accounting)::
and counters in /proc/vmstat consulted for more accurate accounting.
Per-order mTHP collapse statistics are also available under
/sys/kernel/mm/transparent_hugepage/hugepages-<size>kB/stats/)::
/sys/kernel/mm/transparent_hugepage/khugepaged/pages_collapsed

2
Documentation/block/blk-mq.rst
View File

@ -139,7 +139,7 @@ completed.
Further reading
---------------
- `Linux Block IO: Introducing Multi-queue SSD Access on Multi-core Systems <http://kernel.dk/blk-mq.pdf>`_
- `Linux Block IO: Introducing Multi-queue SSD Access on Multi-core Systems <https://www.kernel.dk/blk-mq.pdf>`_
- `NOOP scheduler <https://en.wikipedia.org/wiki/Noop_scheduler>`_

24
Documentation/core-api/maple_tree.rst
View File

@ -17,7 +17,8 @@ supports iterating over a range of entries and going to the previous or next
entry in a cache-efficient manner. The tree can also be put into an RCU-safe
mode of operation which allows reading and writing concurrently. Writers must
synchronize on a lock, which can be the default spinlock, or the user can set
the lock to an external lock of a different type.
the lock to an external lock of a different type. Note that external locks may
interfere with allocations in a low memory situation.
The Maple Tree maintains a small memory footprint and was designed to use
modern processor cache efficiently. The majority of the users will be able to
@ -42,6 +43,15 @@ successful store operation within a given
code segment when allocating cannot be done. Allocations of nodes are
relatively small at around 256 bytes.
Since the maple tree uses internal nodes that are allocated and has rules on
data density, erasing an entry may cause allocations to occur. That is,
erasing an entry may consume memory. Users must take care to ensure that they
do not violate the larger system constraints on when and how memory is
allocated. Most situations are fine to allocate, but the pre-allocation
support is provided as a mechanism to avoid trickier situations. There is also
the possibility of using special entries and clean up the tree later, in
extreme circumstances.
.. _maple-tree-normal-api:
Normal API
@ -63,7 +73,10 @@ success or an error code otherwise. mtree_store_range() works in the same way
but takes a range. mtree_load() is used to retrieve the entry stored at a
given index. You can use mtree_erase() to erase an entire range by only
knowing one value within that range, or mtree_store() call with an entry of
NULL may be used to partially erase a range or many ranges at once.
NULL may be used to partially erase a range or many ranges at once. Note that
mtree_erase() may use GFP_KERNEL | __GFP_NOFAIL for allocations and cannot
fail. mtree_erase() can sleep, so it must not be called from an atomic
context.
If you want to only store a new entry to a range (or index) if that range is
currently ``NULL``, you can use mtree_insert_range() or mtree_insert() which
@ -163,7 +176,10 @@ You can use mas_erase() to erase an entire range by setting index and
last of the maple state to the desired range to erase. This will erase
the first range that is found in that range, set the maple state index
and last as the range that was erased and return the entry that existed
at that location.
at that location. Note that mas_erase() may allocate with the GFP_KERNEL
__GFP_NOFAIL and cannot fail, but may sleep. If this is not okay, consider
using mas_store_gfp() and pass it a ``NULL``,
after setting up the correct range by walking to the entry.
You can walk each entry within a range by using mas_for_each(). If you want
to walk each element of the tree then ``0`` and ``ULONG_MAX`` may be used as
@ -211,7 +227,7 @@ Advanced Locking
The maple tree uses a spinlock by default, but external locks can be used for
tree updates as well. To use an external lock, the tree must be initialized
with the ``MT_FLAGS_LOCK_EXTERN flag``, this is usually done with the
with the ``MT_FLAGS_LOCK_EXTERN`` flag, this is usually done with the
MTREE_INIT_EXT() #define, which takes an external lock as an argument.
Functions and structures

10
Documentation/dev-tools/kmemleak.rst
View File

@ -198,6 +198,16 @@ systems, because of pointers temporarily stored in CPU registers or
stacks. Kmemleak defines MSECS_MIN_AGE (defaulting to 1000) representing
the minimum age of an object to be reported as a memory leak.
The ``min_unref_scans`` module parameter requires an object to be seen
unreferenced in that many consecutive scans before it is reported. It
defaults to 2 when CONFIG_DEBUG_KMEMLEAK_VERBOSE is enabled, where the
periodic scan thread confirms a leak on its own, and to 1 otherwise. A
value of 1 preserves the historical behaviour; higher values filter the
transient false positives described above, at the cost of delaying genuine
reports by up to that many scans. It can be set at boot with
``kmemleak.min_unref_scans=<n>`` or at run-time via
``/sys/module/kmemleak/parameters/min_unref_scans``.
Limitations and Drawbacks
-------------------------

2
Documentation/devicetree/bindings/Makefile
View File

@ -6,7 +6,7 @@ DT_MK_SCHEMA ?= dt-mk-schema
DT_SCHEMA_LINT = $(shell which yamllint || \
echo "warning: python package 'yamllint' not installed, skipping" >&2)
DT_SCHEMA_MIN_VERSION = 2023.9
DT_SCHEMA_MIN_VERSION = 2024.4
PHONY += check_dtschema_version
check_dtschema_version:

14
Documentation/devicetree/bindings/arm/airoha,en7581-chip-scu.yaml
View File

@ -19,15 +19,29 @@ properties:
items:
- enum:
- airoha,en7581-chip-scu
- airoha,an7583-chip-scu
- const: syscon
reg:
maxItems: 1
'#thermal-sensor-cells':
const: 0
required:
- compatible
- reg
if:
properties:
compatible:
contains:
const: airoha,en7581-chip-scu
then:
properties:
'#thermal-sensor-cells': false
additionalProperties: false
examples:

76
Documentation/devicetree/bindings/clock/amlogic,a9-aoclkc.yaml Normal file
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@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2026 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,a9-aoclkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic A9 Series Always-On Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
const: amlogic,a9-aoclkc
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 5
items:
- description: input oscillator
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input sys clk
- description: external fixed 32k (optional)
clock-names:
minItems: 5
items:
- const: xtal
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: sys
- const: ext_32k
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@0 {
compatible = "amlogic,a9-aoclkc";
reg = <0x0 0x0 0x0 0x58>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk 14>,
<&scmi_clk 16>,
<&scmi_clk 18>,
<&scmi_clk 21>;
clock-names = "xtal",
"fdiv3",
"fdiv4",
"fdiv5",
"sys";
};
};

164
Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml Normal file
View File

@ -0,0 +1,164 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2026 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic A9 Series Peripherals Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
const: amlogic,a9-peripherals-clkc
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 27
items:
- description: input oscillator
- description: input fclk div 2
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input fclk div 7
- description: input fclk div 2p5
- description: input sys clk
- description: input gp1 pll
- description: input gp2 pll
- description: input sys pll div 16
- description: input cpu clk div 16
- description: input a78 clk div 16
- description: input dsu clk div 16
- description: input rtc clk
- description: input gp0 pll
- description: input hifi0 pll
- description: input hifi1 pll
- description: input mclk0 pll
- description: input mclk1 pll
- description: input video1 pll
- description: input video2 pll
- description: input hdmi out2 clk
- description: input hdmi pixel clk
- description: input pixel0 pll
- description: input pixel1 pll
- description: input ddr pll test clk
- description: external input rmii oscillator (optional)
clock-names:
minItems: 27
items:
- const: xtal
- const: fdiv2
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: fdiv7
- const: fdiv2p5
- const: sys
- const: gp1
- const: gp2
- const: sysplldiv16
- const: cpudiv16
- const: a78div16
- const: dsudiv16
- const: rtc
- const: gp0
- const: hifi0
- const: hifi1
- const: mclk0
- const: mclk1
- const: vid1
- const: vid2
- const: hdmiout2
- const: hdmipix
- const: pix0
- const: pix1
- const: ddr_test
- const: ext_rmii
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@200 {
compatible = "amlogic,a9-peripherals-clkc";
reg = <0x0 0x200 0x0 0x2f8>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk 10>,
<&scmi_clk 12>,
<&scmi_clk 14>,
<&scmi_clk 16>,
<&scmi_clk 18>,
<&scmi_clk 20>,
<&scmi_clk 21>,
<&scmi_clk 33>,
<&scmi_clk 34>,
<&scmi_clk 35>,
<&scmi_clk 36>,
<&scmi_clk 37>,
<&scmi_clk 38>,
<&scmi_clk 40>,
<&gp0 3>,
<&hifi0 3>,
<&hifi1 3>,
<&mclk0 3>,
<&mclk1 3>,
<&vid1>,
<&vid2>,
<&hdmitx 10>,
<&hdmitx 11>,
<&pix0>,
<&pix1>,
<&ddr 3>;
clock-names = "xtal",
"fdiv2",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"fdiv2p5",
"sys",
"gp1",
"gp2",
"sysplldiv16",
"cpudiv16",
"a78div16",
"dsudiv16",
"rtc",
"gp0",
"hifi0",
"hifi1",
"mclk0",
"mclk1",
"vid1",
"vid2",
"hdmiout2",
"hdmipix",
"pix0",
"pix1",
"ddr_test";
};
};

63
Documentation/devicetree/bindings/clock/eswin,eic7700-hspcrg.yaml Normal file
View File

@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/eswin,eic7700-hspcrg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ESWIN EIC7700 HSP Clock and Reset Generator
maintainers:
- Xuyang Dong <dongxuyang@eswincomputing.com>
description:
Clock and reset generator for the ESWIN EIC7700 HSP (high-speed peripherals).
properties:
compatible:
const: eswin,eic7700-hspcrg
reg:
maxItems: 1
clocks:
items:
- description: HSP configuration top clock
- description: MMC top clock
- description: SATA top clock
clock-names:
items:
- const: cfg
- const: mmc
- const: sata
'#clock-cells':
const: 1
description:
See <dt-bindings/clock/eswin,eic7700-hspcrg.h> for valid indices.
'#reset-cells':
const: 1
description:
See <dt-bindings/reset/eswin,eic7700-hspcrg.h> for valid indices.
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
additionalProperties: false
examples:
- |
clock-controller@50440000 {
compatible = "eswin,eic7700-hspcrg";
reg = <0x50440000 0x2000>;
clocks = <&clock 171>, <&clock 254>, <&clock 187>;
clock-names = "cfg", "mmc", "sata";
#clock-cells = <1>;
#reset-cells = <1>;
};

27
Documentation/devicetree/bindings/clock/keystone-gate.txt
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@ -1,27 +0,0 @@
Binding for Keystone gate control driver which uses PSC controller IP.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,keystone,psc-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : parent clock phandle
- reg : psc control and domain address address space
- reg-names : psc control and domain registers
- domain-id : psc domain id needed to check the transition state register
Optional properties:
- clock-output-names : From common clock binding to override the
default output clock name
Example:
clkusb: clkusb {
#clock-cells = <0>;
compatible = "ti,keystone,psc-clock";
clocks = <&chipclk16>;
clock-output-names = "usb";
reg = <0x02350008 0xb00>, <0x02350000 0x400>;
reg-names = "control", "domain";
domain-id = <0>;
};

70
Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml Normal file
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@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT8173 MFG TOP controller
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description:
The MFG TOP glue layer controls various signals going to the MFG (GPU)
block on the MT8173.
properties:
compatible:
const: mediatek,mt8173-mfgtop
reg:
maxItems: 1
clocks:
maxItems: 4
clock-names:
items:
- const: sys
- const: mem
- const: core
- const: clk26m
power-domains:
maxItems: 1
'#clock-cells':
const: 1
'#power-domain-cells':
const: 0
required:
- compatible
- reg
- clocks
- clock-names
- power-domains
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/mt8173-clk.h>
#include <dt-bindings/power/mt8173-power.h>
clock-controller@13fff000 {
compatible = "mediatek,mt8173-mfgtop";
reg = <0x13fff000 0x1000>;
clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
<&topckgen CLK_TOP_MEM_MFG_IN_SEL>,
<&topckgen CLK_TOP_MFG_SEL>,
<&clk26m>;
clock-names = "sys", "mem", "core", "clk26m";
power-domains = <&spm MT8173_POWER_DOMAIN_MFG>;
#clock-cells = <1>;
#power-domain-cells = <0>;
};

2
Documentation/devicetree/bindings/clock/mediatek,pericfg.yaml
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@ -65,7 +65,7 @@ examples:
- |
pericfg@10003000 {
compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon";
compatible = "mediatek,mt7623-pericfg", "mediatek,mt2701-pericfg", "syscon";
reg = <0x10003000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

1
Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
View File

@ -17,6 +17,7 @@ properties:
compatible:
enum:
- qcom,ipq5018-a53pll
- qcom,ipq5210-a53pll
- qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll

18
Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml
View File

@ -25,19 +25,33 @@ properties:
enum:
- qcom,gcc-mdm9607
clocks:
items:
- description: XO source
- description: Sleep clock source
clock-names:
items:
- const: xo
- const: sleep_clk
required:
- compatible
- clocks
- clock-names
- '#power-domain-cells'
unevaluatedProperties: false
examples:
- |
clock-controller@900000 {
clock-controller@1800000 {
compatible = "qcom,gcc-mdm9607";
reg = <0x900000 0x4000>;
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo_board>, <&sleep_clk>;
clock-names = "xo", "sleep_clk";
};
...

8
Documentation/devicetree/bindings/clock/qcom,glymur-gcc.yaml
View File

@ -65,9 +65,15 @@ properties:
- description: USB4 PHY 2 pcie pipe clock source
- description: USB4 PHY 2 Max pipe clock source
power-domains:
description:
A phandle and PM domain specifier for the CX power domain.
maxItems: 1
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@ -78,6 +84,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@100000 {
compatible = "qcom,glymur-gcc";
reg = <0x100000 0x1f9000>;
@ -113,6 +120,7 @@ examples:
<&usb4_phy_0_pcie_pipe>, <&usb4_phy_0_max_pipe>,
<&usb4_phy_1_pcie_pipe>, <&usb4_phy_1_max_pipe>,
<&usb4_phy_2_pcie_pipe>, <&usb4_phy_2_max_pipe>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

146
Documentation/devicetree/bindings/clock/qcom,glymur-tcsr.yaml Normal file
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@ -0,0 +1,146 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,glymur-tcsr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm TCSR Clock Controller on Glymur
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm TCSR clock control module provides the clocks, resets and
power domains on Glymur
See also:
- include/dt-bindings/clock/qcom,glymur-tcsr.h
properties:
compatible:
items:
- enum:
- qcom,glymur-tcsr
- qcom,mahua-tcsr
- const: syscon
clocks:
items:
- description: TCXO pad clock
reg:
maxItems: 1
'#clock-cells':
const: 1
'#reset-cells':
const: 1
vdda-qrefrpt0-0p9-supply: true
vdda-qrefrpt1-0p9-supply: true
vdda-qrefrpt2-0p9-supply: true
vdda-qrefrpt3-0p9-supply: true
vdda-qrefrpt4-0p9-supply: true
vdda-qrefrpt5-0p9-supply: true
vdda-qrefrx0-0p9-supply: true
vdda-qrefrx1-0p9-supply: true
vdda-qrefrx2-0p9-supply: true
vdda-qrefrx3-0p9-supply: true
vdda-qrefrx4-0p9-supply: true
vdda-qrefrx5-0p9-supply: true
vdda-qreftx0-0p9-supply: true
vdda-qreftx0-1p2-supply: true
vdda-qreftx1-0p9-supply: true
vdda-refgen3-0p9-supply: true
vdda-refgen3-1p2-supply: true
vdda-refgen4-0p9-supply: true
vdda-refgen4-1p2-supply: true
allOf:
- if:
properties:
compatible:
contains:
const: qcom,glymur-tcsr
then:
required:
- vdda-qrefrpt0-0p9-supply
- vdda-qrefrpt1-0p9-supply
- vdda-qrefrpt2-0p9-supply
- vdda-qrefrpt3-0p9-supply
- vdda-qrefrpt4-0p9-supply
- vdda-qrefrx0-0p9-supply
- vdda-qrefrx1-0p9-supply
- vdda-qrefrx2-0p9-supply
- vdda-qrefrx4-0p9-supply
- vdda-qrefrx5-0p9-supply
- vdda-qreftx0-0p9-supply
- vdda-qreftx0-1p2-supply
- vdda-qreftx1-0p9-supply
- vdda-refgen3-0p9-supply
- vdda-refgen3-1p2-supply
- vdda-refgen4-0p9-supply
- vdda-refgen4-1p2-supply
- if:
properties:
compatible:
contains:
const: qcom,mahua-tcsr
then:
required:
- vdda-qrefrpt0-0p9-supply
- vdda-qrefrpt1-0p9-supply
- vdda-qrefrpt2-0p9-supply
- vdda-qrefrpt3-0p9-supply
- vdda-qrefrpt4-0p9-supply
- vdda-qrefrpt5-0p9-supply
- vdda-qrefrx1-0p9-supply
- vdda-qrefrx2-0p9-supply
- vdda-qrefrx3-0p9-supply
- vdda-qreftx1-0p9-supply
- vdda-refgen3-0p9-supply
- vdda-refgen3-1p2-supply
required:
- compatible
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@1fd5000 {
compatible = "qcom,glymur-tcsr", "syscon";
reg = <0x0 0x1fd5000 0x0 0x21000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
vdda-qrefrpt0-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt1-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt2-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt3-0p9-supply = <&vreg_l1a>;
vdda-qrefrpt4-0p9-supply = <&vreg_l1a>;
vdda-qrefrx0-0p9-supply = <&vreg_l1a>;
vdda-qrefrx1-0p9-supply = <&vreg_l1a>;
vdda-qrefrx2-0p9-supply = <&vreg_l1a>;
vdda-qrefrx4-0p9-supply = <&vreg_l1a>;
vdda-qrefrx5-0p9-supply = <&vreg_l1a>;
vdda-qreftx0-0p9-supply = <&vreg_l1a>;
vdda-qreftx0-1p2-supply = <&vreg_l2a>;
vdda-qreftx1-0p9-supply = <&vreg_l1a>;
vdda-refgen3-0p9-supply = <&vreg_l1a>;
vdda-refgen3-1p2-supply = <&vreg_l2a>;
vdda-refgen4-0p9-supply = <&vreg_l1a>;
vdda-refgen4-1p2-supply = <&vreg_l2a>;
};
};
...

11
Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml
View File

@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Hawi
maintainers:
- Vivek Aknurwar <vivek.aknurwar@oss.qualcomm.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Hawi.
domains on Hawi and Maili.
See also: include/dt-bindings/clock/qcom,hawi-gcc.h
See also:
include/dt-bindings/clock/qcom,hawi-gcc.h
include/dt-bindings/clock/qcom,maili-gcc.h
properties:
compatible:
const: qcom,hawi-gcc
enum:
- qcom,hawi-gcc
- qcom,maili-gcc
clocks:
items:

15
Documentation/devicetree/bindings/clock/qcom,qcm2290-dispcc.yaml
View File

@ -17,7 +17,13 @@ description: |
properties:
compatible:
const: qcom,qcm2290-dispcc
oneOf:
- items:
- enum:
- qcom,shikra-dispcc
- const: qcom,qcm2290-dispcc
- enum:
- qcom,qcm2290-dispcc
clocks:
items:
@ -37,10 +43,15 @@ properties:
- const: dsi0_phy_pll_out_byteclk
- const: dsi0_phy_pll_out_dsiclk
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- clock-names
- power-domains
- '#power-domain-cells'
allOf:
@ -53,6 +64,7 @@ examples:
#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
clock-controller@5f00000 {
compatible = "qcom,qcm2290-dispcc";
reg = <0x5f00000 0x20000>;
@ -68,6 +80,7 @@ examples:
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk";
power-domains = <&rpmpd RPMPD_VDDCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;

4
Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml
View File

@ -18,7 +18,9 @@ description: |
properties:
compatible:
const: qcom,qcm2290-gpucc
enum:
- qcom,qcm2290-gpucc
- qcom,shikra-gpucc
reg:
maxItems: 1

65
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
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@ -16,36 +16,41 @@ description: |
properties:
compatible:
enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,hawi-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
- qcom,sar2130p-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
- qcom,sc8280xp-rpmh-clk
- qcom,sdm670-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,sm8750-rpmh-clk
- qcom,x1e80100-rpmh-clk
oneOf:
- enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,hawi-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
- qcom,sar2130p-rpmh-clk
- qcom,sc7180-rpmh-clk
- qcom,sc7280-rpmh-clk
- qcom,sc8180x-rpmh-clk
- qcom,sc8280xp-rpmh-clk
- qcom,sdm670-rpmh-clk
- qcom,sdm845-rpmh-clk
- qcom,sdx55-rpmh-clk
- qcom,sdx65-rpmh-clk
- qcom,sdx75-rpmh-clk
- qcom,sm4450-rpmh-clk
- qcom,sm6350-rpmh-clk
- qcom,sm8150-rpmh-clk
- qcom,sm8250-rpmh-clk
- qcom,sm8350-rpmh-clk
- qcom,sm8450-rpmh-clk
- qcom,sm8550-rpmh-clk
- qcom,sm8650-rpmh-clk
- qcom,sm8750-rpmh-clk
- qcom,x1e80100-rpmh-clk
- items:
- enum:
- qcom,maili-rpmh-clk
- const: qcom,hawi-rpmh-clk
clocks:
maxItems: 1

55
Documentation/devicetree/bindings/clock/qcom,shikra-audiocorecc.yaml Normal file
View File

@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,shikra-audiocorecc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Audio Core Clock Controller for Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
description: |
Audio core clock control module provides the clocks on Qualcomm Shikra
SoC platform.
See also:
- include/dt-bindings/clock/qcom,shikra-audiocorecc.h
properties:
compatible:
const: qcom,shikra-audiocorecc
clocks:
items:
- description: Board XO source
- description: Board sleep clock
- description: Audio ref clock source
reg:
maxItems: 1
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
clock-controller@a0a0000 {
compatible = "qcom,shikra-audiocorecc";
reg = <0x0a0a0000 0x10000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<&aud_ref_clk_src>;
#clock-cells = <1>;
};
...

12
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@ -70,13 +70,11 @@ allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
not:
contains:
enum:
- qcom,sm8475-camcc
- qcom,sm8650-camcc
then:
required:
- required-opps

4
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@ -18,6 +18,8 @@ description: |
include/dt-bindings/clock/qcom,glymur-gpucc.h
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,nord-gpu2cc.h
include/dt-bindings/clock/qcom,nord-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
include/dt-bindings/clock/qcom,sm4450-gpucc.h
include/dt-bindings/clock/qcom,sm8450-gpucc.h
@ -33,6 +35,8 @@ properties:
- qcom,glymur-gpucc
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,nord-gpu2cc
- qcom,nord-gpucc
- qcom,sar2130p-gpucc
- qcom,sm4450-gpucc
- qcom,sm8450-gpucc

17
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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@ -16,7 +16,9 @@ description: |
See also:
include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,hawi-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,maili-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@ -26,7 +28,9 @@ properties:
compatible:
enum:
- qcom,glymur-videocc
- qcom,hawi-videocc
- qcom,kaanapali-videocc
- qcom,maili-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
@ -65,14 +69,11 @@ allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
- qcom,x1p42100-videocc
not:
contains:
enum:
- qcom,sm8475-videocc
- qcom,sm8650-videocc
then:
required:
- required-opps

3
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@ -16,6 +16,7 @@ description: |
See also:
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,nord-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
@ -25,6 +26,8 @@ properties:
compatible:
enum:
- qcom,kaanapali-dispcc
- qcom,nord-dispcc0
- qcom,nord-dispcc1
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc

34
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
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@ -16,7 +16,6 @@ description: |
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,hawi-tcsrcc.h
- include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
@ -25,20 +24,25 @@ description: |
properties:
compatible:
items:
- enum:
- qcom,eliza-tcsr
- qcom,glymur-tcsr
- qcom,hawi-tcsrcc
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon
oneOf:
- items:
- enum:
- qcom,eliza-tcsr
- qcom,hawi-tcsrcc
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,sm8750-tcsr
- qcom,x1e80100-tcsr
- const: syscon
- items:
- enum:
- qcom,maili-tcsrcc
- const: qcom,hawi-tcsrcc
- const: syscon
clocks:
items:

55
Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml Normal file
View File

@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car X5H Clock Pulse Generator
maintainers:
- Geert Uytterhoeven <geert+renesas@glider.be>
description:
The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillators,
PLL circuits, clock dividers and clock control circuits. It provides various
clocks for other modules.
properties:
compatible:
const: renesas,r8a78000-cpg
reg:
maxItems: 1
clocks:
maxItems: 2
clock-names:
items:
- const: extal
- const: extalr
'#clock-cells':
description:
The single clock specifier cell must be the clock number, as defined in
<dt-bindings/clock/renesas,r8a78000-cpg.h>.
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@c1320000 {
compatible = "renesas,r8a78000-cpg";
reg = <0xc1320000 0x10000>;
clocks = <&extal_clk>, <&extalr_clk>;
clock-names = "extal", "extalr";
#clock-cells = <1>;
};

6
Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
View File

@ -26,16 +26,22 @@ properties:
maxItems: 1
clocks:
minItems: 3
items:
- description: AUDIO_EXTAL clock input
- description: RTXIN clock input
- description: QEXTAL clock input
- description: AUDIO_CLKB clock input
- description: AUDIO_CLKC clock input
clock-names:
minItems: 3
items:
- const: audio_extal
- const: rtxin
- const: qextal
- const: audio_clkb
- const: audio_clkc
'#clock-cells':
description: |

2
Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml
View File

@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Versaclock7 Programmable Clock
maintainers:
- Alex Helms <alexander.helms.jy@renesas.com>
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
Renesas Versaclock7 is a family of configurable clock generator and

60
Documentation/devicetree/bindings/clock/rockchip,rv1106-cru.yaml Normal file
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@ -0,0 +1,60 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rv1106-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RV1106 Clock and Reset Unit
maintainers:
- Simon Glass <sjg@chromium.org>
- Heiko Stuebner <heiko@sntech.de>
description:
The RV1106 clock controller generates the clock and also implements a
reset controller for SoC peripherals.
properties:
compatible:
const: rockchip,rv1106-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks:
maxItems: 1
clock-names:
const: xin24m
rockchip,grf:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the syscon managing the "general register files" (GRF).
If missing, pll rates are not changeable due to the missing pll
lock status, and the MMC drive and sample phase clocks, whose
control registers live in the GRF region, are not registered.
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@ff3b0000 {
compatible = "rockchip,rv1106-cru";
reg = <0xff3b0000 0x20000>;
rockchip,grf = <&grf>;
#clock-cells = <1>;
#reset-cells = <1>;
};

10
Documentation/devicetree/bindings/clock/silabs,si544.yaml
View File

@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/silabs,si544.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Labs SI514/SI544 clock generator
title: Silicon Labs SI514/SI544/SI549 clock generator
maintainers:
- Mike Looijmans <mike.looijmans@topic.nl>
@ -13,8 +13,9 @@ description: >
Silicon Labs 514/544 programmable I2C clock generator. Details about the device
can be found in the datasheet:
https://www.silabs.com/Support%20Documents/TechnicalDocs/si514.pdf
https://www.silabs.com/documents/public/data-sheets/si544-datasheet.pdf
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si514.pdf
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si544-datasheet.pdf
https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/si549-datasheet.pdf
properties:
compatible:
@ -23,6 +24,9 @@ properties:
- silabs,si544a
- silabs,si544b
- silabs,si544c
- silabs,si549a
- silabs,si549b
- silabs,si549c
reg:
maxItems: 1

140
Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml
View File

@ -125,75 +125,75 @@ examples:
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APB5>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APB5>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>;
};
...

160
Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml
View File

@ -135,85 +135,85 @@ examples:
reg = <0x44200000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_ICN_VID>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_15>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_28>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_32>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_34>,
<&scmi_clk CK_SCMI_FLEXGEN_35>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_49>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_59>,
<&scmi_clk CK_SCMI_FLEXGEN_60>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_MSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>,
<&scmi_clk CK_SCMI_HSE_DIV2>,
<&scmi_clk CK_SCMI_ICN_HS_MCU>,
<&scmi_clk CK_SCMI_ICN_LS_MCU>,
<&scmi_clk CK_SCMI_ICN_SDMMC>,
<&scmi_clk CK_SCMI_ICN_DDR>,
<&scmi_clk CK_SCMI_ICN_DISPLAY>,
<&scmi_clk CK_SCMI_ICN_HSL>,
<&scmi_clk CK_SCMI_ICN_NIC>,
<&scmi_clk CK_SCMI_ICN_VID>,
<&scmi_clk CK_SCMI_FLEXGEN_07>,
<&scmi_clk CK_SCMI_FLEXGEN_08>,
<&scmi_clk CK_SCMI_FLEXGEN_09>,
<&scmi_clk CK_SCMI_FLEXGEN_10>,
<&scmi_clk CK_SCMI_FLEXGEN_11>,
<&scmi_clk CK_SCMI_FLEXGEN_12>,
<&scmi_clk CK_SCMI_FLEXGEN_13>,
<&scmi_clk CK_SCMI_FLEXGEN_14>,
<&scmi_clk CK_SCMI_FLEXGEN_15>,
<&scmi_clk CK_SCMI_FLEXGEN_16>,
<&scmi_clk CK_SCMI_FLEXGEN_17>,
<&scmi_clk CK_SCMI_FLEXGEN_18>,
<&scmi_clk CK_SCMI_FLEXGEN_19>,
<&scmi_clk CK_SCMI_FLEXGEN_20>,
<&scmi_clk CK_SCMI_FLEXGEN_21>,
<&scmi_clk CK_SCMI_FLEXGEN_22>,
<&scmi_clk CK_SCMI_FLEXGEN_23>,
<&scmi_clk CK_SCMI_FLEXGEN_24>,
<&scmi_clk CK_SCMI_FLEXGEN_25>,
<&scmi_clk CK_SCMI_FLEXGEN_26>,
<&scmi_clk CK_SCMI_FLEXGEN_27>,
<&scmi_clk CK_SCMI_FLEXGEN_28>,
<&scmi_clk CK_SCMI_FLEXGEN_29>,
<&scmi_clk CK_SCMI_FLEXGEN_30>,
<&scmi_clk CK_SCMI_FLEXGEN_31>,
<&scmi_clk CK_SCMI_FLEXGEN_32>,
<&scmi_clk CK_SCMI_FLEXGEN_33>,
<&scmi_clk CK_SCMI_FLEXGEN_34>,
<&scmi_clk CK_SCMI_FLEXGEN_35>,
<&scmi_clk CK_SCMI_FLEXGEN_36>,
<&scmi_clk CK_SCMI_FLEXGEN_37>,
<&scmi_clk CK_SCMI_FLEXGEN_38>,
<&scmi_clk CK_SCMI_FLEXGEN_39>,
<&scmi_clk CK_SCMI_FLEXGEN_40>,
<&scmi_clk CK_SCMI_FLEXGEN_41>,
<&scmi_clk CK_SCMI_FLEXGEN_42>,
<&scmi_clk CK_SCMI_FLEXGEN_43>,
<&scmi_clk CK_SCMI_FLEXGEN_44>,
<&scmi_clk CK_SCMI_FLEXGEN_45>,
<&scmi_clk CK_SCMI_FLEXGEN_46>,
<&scmi_clk CK_SCMI_FLEXGEN_47>,
<&scmi_clk CK_SCMI_FLEXGEN_48>,
<&scmi_clk CK_SCMI_FLEXGEN_49>,
<&scmi_clk CK_SCMI_FLEXGEN_50>,
<&scmi_clk CK_SCMI_FLEXGEN_51>,
<&scmi_clk CK_SCMI_FLEXGEN_52>,
<&scmi_clk CK_SCMI_FLEXGEN_53>,
<&scmi_clk CK_SCMI_FLEXGEN_54>,
<&scmi_clk CK_SCMI_FLEXGEN_55>,
<&scmi_clk CK_SCMI_FLEXGEN_56>,
<&scmi_clk CK_SCMI_FLEXGEN_57>,
<&scmi_clk CK_SCMI_FLEXGEN_58>,
<&scmi_clk CK_SCMI_FLEXGEN_59>,
<&scmi_clk CK_SCMI_FLEXGEN_60>,
<&scmi_clk CK_SCMI_FLEXGEN_61>,
<&scmi_clk CK_SCMI_FLEXGEN_62>,
<&scmi_clk CK_SCMI_FLEXGEN_63>,
<&scmi_clk CK_SCMI_ICN_APB1>,
<&scmi_clk CK_SCMI_ICN_APB2>,
<&scmi_clk CK_SCMI_ICN_APB3>,
<&scmi_clk CK_SCMI_ICN_APB4>,
<&scmi_clk CK_SCMI_ICN_APBDBG>,
<&scmi_clk CK_SCMI_TIMG1>,
<&scmi_clk CK_SCMI_TIMG2>,
<&scmi_clk CK_SCMI_PLL3>,
<&clk_dsi_txbyte>;
};
...

60
Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml Normal file
View File

@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti,keystone,psc-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Keystone PSC clock
maintainers:
- Santosh Shilimkar <santosh.shilimkar@ti.com>
- Murali Karicheri <m-karicheri2@ti.com>
properties:
compatible:
const: ti,keystone,psc-clock
reg:
items:
- description: PSC control
- description: Domain
reg-names:
items:
- const: control
- const: domain
domain-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: PSC domain id needed to check the transition state register
clocks:
maxItems: 1
clock-output-names:
maxItems: 1
"#clock-cells":
const: 0
required:
- compatible
- reg
- reg-names
- domain-id
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
clkusb@2350008 {
compatible = "ti,keystone,psc-clock";
reg = <0x02350008 0xb00>, <0x02350000 0x400>;
reg-names = "control", "domain";
domain-id = <0>;
clocks = <&chipclk16>;
clock-output-names = "usb";
#clock-cells = <0>;
};

43
Documentation/devicetree/bindings/clock/ti/apll.txt
View File

@ -1,43 +0,0 @@
Binding for Texas Instruments APLL clock.
This binding uses the common clock binding[1]. It assumes a
register-mapped APLL with usually two selectable input clocks
(reference clock and bypass clock), with analog phase locked
loop logic for multiplying the input clock to a desired output
clock. This clock also typically supports different operation
modes (locked, low power stop etc.) APLL mostly behaves like
a subtype of a DPLL [2], although a simplified one at that.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/clock/ti/dpll.txt
Required properties:
- compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of parent clocks (clk-ref and clk-bypass)
- reg : address and length of the register set for controlling the APLL.
It contains the information of registers in the following order:
"control" - contains the control register offset
"idlest" - contains the idlest register offset
"autoidle" - contains the autoidle register offset (OMAP2 only)
- ti,clock-frequency : static clock frequency for the clock (OMAP2 only)
- ti,idlest-shift : bit-shift for the idlest field (OMAP2 only)
- ti,bit-shift : bit-shift for enable and autoidle fields (OMAP2 only)
Examples:
apll_pcie_ck: apll_pcie_ck {
#clock-cells = <0>;
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
compatible = "ti,dra7-apll-clock";
};
apll96_ck: apll96_ck {
#clock-cells = <0>;
compatible = "ti,omap2-apll-clock";
clocks = <&sys_ck>;
ti,bit-shift = <2>;
ti,idlest-shift = <8>;
ti,clock-frequency = <96000000>;
reg = <0x0500>, <0x0530>, <0x0520>;
};

25
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@ -1,25 +0,0 @@
Binding for Texas Instruments clockdomain.
This binding uses the common clock binding[1] in consumer role.
Every clock on TI SoC belongs to one clockdomain, but software
only needs this information for specific clocks which require
their parent clockdomain to be controlled when the clock is
enabled/disabled. This binding doesn't define a new clock
binding type, it is used to group existing clock nodes under
hardware hierarchy.
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "ti,clockdomain"
- #clock-cells : from common clock binding; shall be set to 0.
- clocks : link phandles of clocks within this domain
Optional properties:
- clock-output-names : from common clock binding.
Examples:
dss_clkdm: dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
};

89
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@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti/ti,apll-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments APLL clock
maintainers:
- Eduard Bostina <egbostina@gmail.com>
allOf:
- $ref: /schemas/clock/clock.yaml#
description:
This binding assumes a register-mapped APLL with usually two selectable
input clocks (reference clock and bypass clock), with analog phase locked
loop logic for multiplying the input clock to a desired output clock.
This clock also typically supports different operation modes (locked, low
power stop etc.) APLL mostly behaves like a subtype of a DPLL, although
a simplified one at that.
properties:
compatible:
enum:
- ti,dra7-apll-clock
- ti,omap2-apll-clock
"#clock-cells":
const: 0
clocks:
minItems: 1
maxItems: 2
description: Link phandles of parent clocks (clk-ref and clk-bypass)
reg:
minItems: 2
maxItems: 3
description: |
Address and length of the register set for controlling the APLL.
It contains the information of registers in the following order:
"control" - contains the control register offset
"idlest" - contains the idlest register offset
"autoidle" - contains the autoidle register offset (OMAP2 only)
ti,clock-frequency:
$ref: /schemas/types.yaml#/definitions/uint32
description: static clock frequency for the clock (OMAP2 only)
ti,idlest-shift:
$ref: /schemas/types.yaml#/definitions/uint32
description: bit-shift for the idlest field (OMAP2 only)
ti,bit-shift:
$ref: /schemas/types.yaml#/definitions/uint32
description: bit-shift for enable and autoidle fields (OMAP2 only)
required:
- compatible
- "#clock-cells"
- clocks
- reg
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <1>;
#size-cells = <0>;
clock@21c {
#clock-cells = <0>;
compatible = "ti,dra7-apll-clock";
clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
reg = <0x021c>, <0x0220>;
};
clock@500 {
#clock-cells = <0>;
compatible = "ti,omap2-apll-clock";
clocks = <&sys_ck>;
ti,bit-shift = <2>;
ti,idlest-shift = <8>;
ti,clock-frequency = <96000000>;
reg = <0x0500>, <0x0530>, <0x0520>;
};
};

44
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@ -0,0 +1,44 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti/ti,clockdomain.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments clockdomain
maintainers:
- Tero Kristo <kristo@kernel.org>
description:
This binding uses the common clock binding in consumer role. Every clock on TI
SoC belongs to one clockdomain, but software only needs this information for
specific clocks which require their parent clockdomain to be controlled when
the clock is enabled/disabled. This binding doesn't define a new clock binding
type, it is used to group existing clock nodes under hardware hierarchy.
properties:
compatible:
const: ti,clockdomain
"#clock-cells":
const: 0
clocks:
minItems: 1
maxItems: 64
clock-output-names:
maxItems: 1
required:
- compatible
- clocks
additionalProperties: false
examples:
- |
dss_clkdm {
compatible = "ti,clockdomain";
clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
};

2
Documentation/devicetree/bindings/clock/ti/ti,gate-clock.yaml
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@ -19,7 +19,7 @@ description: |
that is used.
[1] Documentation/devicetree/bindings/clock/gpio-gate-clock.yaml
[2] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
[2] Documentation/devicetree/bindings/clock/ti/ti,clockdomain.yaml
properties:
compatible:

60
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@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ultrarisc,dp1000-clk.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UltraRISC DP1000 Clock Controller
maintainers:
- Jia Wang <wangjia@ultrarisc.com>
description: |
The UltraRISC DP1000 clock controller is driven from a single external
oscillator input. It provides a system PLL with fractional multiplier
and post-divider stages, several fixed-ratio derived clocks for
the on-chip subsystem, Clock Configuration Register (CCR) divider
outputs for GMAC and the UART, I2C, and SPI root clocks, and
per-instance gate clocks for UART0-3, I2C0-3, and SPI0-1.
All available clocks are defined as preprocessor macros in
include/dt-bindings/clock/ultrarisc,dp1000-clk.h
properties:
compatible:
const: ultrarisc,dp1000-clk
reg:
maxItems: 1
clocks:
maxItems: 1
description:
External oscillator input clock used as the parent of the PLLs.
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/ultrarisc,dp1000-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@11080000 {
compatible = "ultrarisc,dp1000-clk";
reg = <0x0 0x11080000 0x0 0x1000>;
clocks = <&osc>;
#clock-cells = <1>;
};
};

2
Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml
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@ -70,7 +70,7 @@ additionalProperties: false
examples:
- |
clock-controller@b0000000 {
clock-controller@b0000000 {
compatible = "xlnx,clocking-wizard";
reg = <0xb0000000 0x10000>;
#clock-cells = <1>;

4
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
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@ -47,6 +47,10 @@ properties:
- qcom,sm8650-dsi-ctrl
- qcom,sm8750-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
- items:
- const: qcom,shikra-dsi-ctrl
- const: qcom,qcm2290-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
- items:
- enum:
- qcom,qcs8300-dsi-ctrl

1
Documentation/devicetree/bindings/display/msm/gmu.yaml
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@ -262,6 +262,7 @@ allOf:
compatible:
contains:
enum:
- qcom,adreno-gmu-722.0
- qcom,adreno-gmu-730.1
- qcom,adreno-gmu-740.1
- qcom,adreno-gmu-750.1

4
Documentation/devicetree/bindings/display/msm/gpu.yaml
View File

@ -353,6 +353,7 @@ allOf:
- qcom,adreno-610.0
- qcom,adreno-619.1
- qcom,adreno-07000200
- qcom,adreno-07000400
then:
properties:
clocks:
@ -413,6 +414,7 @@ allOf:
contains:
enum:
- qcom,adreno-44010000
- qcom,adreno-44050a01
- qcom,adreno-44070001
then:
properties:
@ -443,11 +445,13 @@ allOf:
- qcom,adreno-680.1
- qcom,adreno-690.0
- qcom,adreno-730.1
- qcom,adreno-43020100
- qcom,adreno-43030c00
- qcom,adreno-43050a01
- qcom,adreno-43050c01
- qcom,adreno-43051401
- qcom,adreno-44010000
- qcom,adreno-44050a01
- qcom,adreno-44070001
then: # Starting with A6xx, the clocks are usually defined in the GMU node

6
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-dpu.yaml
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@ -13,7 +13,11 @@ $ref: /schemas/display/msm/dpu-common.yaml#
properties:
compatible:
const: qcom,qcm2290-dpu
oneOf:
- const: qcom,qcm2290-dpu
- items:
- const: qcom,shikra-dpu
- const: qcom,qcm2290-dpu
reg:
items:

19
Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml
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@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/display/msm/qcom,qcm2290-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QCM220 Display MDSS
title: Qualcomm QCM2290 and Shikra Display MDSS
maintainers:
- Loic Poulain <loic.poulain@linaro.org>
@ -12,13 +12,18 @@ maintainers:
description:
Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
sub-blocks like DPU display controller and DSI. Device tree bindings of MDSS
are mentioned for QCM2290 target.
are mentioned for QCM2290 and Shikra targets. Shikra uses the same MDSS/DPU/DSI
hardware as QCM2290 (DPU 6.5) and shares the same register layout.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
const: qcom,qcm2290-mdss
oneOf:
- const: qcom,qcm2290-mdss
- items:
- const: qcom,shikra-mdss
- const: qcom,qcm2290-mdss
clocks:
items:
@ -52,7 +57,8 @@ patternProperties:
properties:
compatible:
const: qcom,qcm2290-dpu
contains:
const: qcom,qcm2290-dpu
"^dsi@[0-9a-f]+$":
type: object
@ -60,9 +66,8 @@ patternProperties:
properties:
compatible:
items:
- const: qcom,qcm2290-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
contains:
const: qcom,qcm2290-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object

116
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@ -0,0 +1,116 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/input/qcom,spmi-haptics.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Haptics device inside Qualcomm Technologies, Inc. PMIC
maintainers:
- Fenglin Wu <fenglin.wu@oss.qualcomm.com>
description: |
Certain Qualcomm PMICs integrate a haptics module, such as the HAP530_HV haptics
module in the PMIH0108 PMIC, which drives an LRA (Linear Resonant Actuator) with
an output voltage up to 10 V. Several play modes are supported in HAP530_HV:
DIRECT_PLAY: The hardware outputs sinusoidal waveforms whose period is
defined by qcom,lra-period-us and whose peak voltage is defined by
qcom,vmax-microvolt. The driving amplitude can be scaled in the range
[0, 255] via a single register byte. Hardware-based LRA auto-resonance
tracking is enabled by default in this mode, allowing the haptics engine
to follow the actual resonant frequency of the LRA and update the driving
period accordingly to achieve stronger vibration magnitude.
FIFO: The hardware can play an arbitrary waveform composed of a sequence
of 8-bit samples at a configurable play rate. Samples are pre-filled
into the internal FIFO memory of the haptics module and continuously
replenished via the FIFO-empty IRQ until all samples have been played.
An 8K-byte FIFO memory bank is available in the HAP530_HV haptics module,
shared between the FIFO and PAT_MEM play modes. The memory partition
between the two modes is configurable via registers, and FIFO mode always
uses the 1st partition starting from offset 0.
PAT_MEM: This mode is very similar to FIFO streaming mode but without the
data refilling capability. It is designed mainly for short, latency-critical
vibrations. The memory space for PAT_MEM mode must be reserved for dedicated
usage, and the waveform data should be preloaded and remain unchanged
thereafter. The haptics module can play the waveform data from the memory
region specified by the PAT_MEM play start address and length registers.
In either FIFO mode or PAT_MEM mode, the following play rates are supported:
-- 0(T_LRA): each FIFO byte drives one full sinusoidal cycle with the
period defined in qcom,lra-period-us.
-- 1/2/3(T_LRA_DIV_2/4/8): each FIFO byte drives a half/quarter/eighth
sinusoidal cycle with the period defined in qcom,lra-period-us.
-- 4/5/6(T_LRA_X_2/4/8): each FIFO byte drives 2/4/8 sinusoidal cycles
with the period defined in qcom,lra-period-us.
-- 8/9/10/11/12/13(8KHz/16KHz/24KHz/32KHz/44.1KHz/48KHz): the FIFO
data is treated as PCM samples and drives the output with an
arbitrarily shaped waveform. This mode is typically used to define
custom driving waveforms for specific vibration effects such as fast
attack, crisp brake, etc.
The drive voltage in FIFO or PAT_MEM mode can exceed the value defined in
qcom,vmax-microvolt to achieve a special vibration effect, but the waveform
must be short enough to prevent the LRA from being damaged by operating at
an overvoltage.
Also, hardware-based LRA auto-resonance tracking is normally disabled in
FIFO or PAT_MEM mode, as these modes are intended to drive arbitrary
waveforms that may not follow the resonant frequency; autonomous hardware
resonance correction would interfere with the intended output.
properties:
compatible:
items:
- const: qcom,pmih0108-haptics
- const: qcom,spmi-haptics
reg:
items:
- description: HAP_CFG module base address
- description: HAP_PTN module base address
reg-names:
items:
- const: cfg
- const: ptn
interrupts:
maxItems: 1
interrupt-names:
items:
- const: fifo-empty
qcom,vmax-microvolt:
description:
Maximum allowed output driving voltage in microvolts, must be a multiple
of 50,000 uV. This is the peak driving voltage in DIRECT_PLAY mode,
which outputs sinusoidal waveforms. The value should be equal to the
square root of 2 times the Vrms voltage of the LRA.
minimum: 50000
maximum: 10000000
multipleOf: 50000
qcom,lra-period-us:
description:
LRA actuator initial resonance period in microseconds
(1,000,000 / resonant_freq_hz). Used to configure T_LRA-based play
rates and the auto-resonance zero-crossing window. It could be also used
as the initial period if the LRA wants to be driven off resonance.
minimum: 5
maximum: 20475
multipleOf: 5
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- qcom,vmax-microvolt
- qcom,lra-period-us
additionalProperties: false

133
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@ -0,0 +1,133 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/adi,ltc3220.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analog Devices LTC3220 LED Driver
maintainers:
- Edelweise Escala <edelweise.escala@analog.com>
description: >
The LTC3220 is a multi-display LED driver, which contains a high-efficiency,
low-noise charge pump to provide power to up to 18 LED current sources.
The LEDs are individually configurable to 64-step linear brightness control,
blinking and gradation control via 2-wire I2C interface.
For more product information please see the link below
https://www.analog.com/en/products/ltc3220.html
properties:
compatible:
const: adi,ltc3220
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
reset-gpios:
maxItems: 1
patternProperties:
'^led@([1-9a-f]|1[0-2])$':
type: object
$ref: /schemas/leds/common.yaml#
unevaluatedProperties: false
properties:
reg:
description:
Output channel for the LED (1-18 maps to LED outputs D1-D18).
Unit-address must be in hexadecimal (1-12 hex = 1-18 decimal).
For aggregated LED control, define only one LED node with reg = <0x1>
and use led-sources to list all controlled outputs. Only reg 1 should
be present when using led-sources.
items:
- minimum: 1
maximum: 18
required:
- reg
if:
required:
- led-sources
then:
properties:
reg:
items:
- const: 1
required:
- compatible
- reg
- '#address-cells'
- '#size-cells'
additionalProperties: false
examples:
- |
// Independent LEDs
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
led-controller@1c {
compatible = "adi,ltc3220";
reg = <0x1c>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
led@1 {
reg = <0x1>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <1>;
};
led@2 {
reg = <0x2>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <2>;
};
led@3 {
reg = <0x3>;
function = LED_FUNCTION_INDICATOR;
function-enumerator = <3>;
};
};
};
- |
// Aggregated LED
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
led-controller@1c {
compatible = "adi,ltc3220";
reg = <0x1c>;
#address-cells = <1>;
#size-cells = <0>;
led@1 {
reg = <0x1>;
led-sources = <0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12>;
function = LED_FUNCTION_BACKLIGHT;
};
};
};
...

1
Documentation/devicetree/bindings/leds/backlight/88pm860x.txt
View File

@ -13,3 +13,4 @@ Example:
};
backlight-2 {
};
};

2
Documentation/devicetree/bindings/leds/backlight/awinic,aw99706.yaml
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@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Awinic AW99706 6-channel WLED Backlight Driver
maintainers:
- Junjie Cao <caojunjie650@gmail.com>
- Junjie Cao <junjie.cao@linux.dev>
allOf:
- $ref: common.yaml#

52
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@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/backlight/silergy,sy7758.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silergy SY7758 6-channel High Efficiency LED Driver
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
description:
Silergy SY7758 is a high efficiency 6-channels LED backlight
driver with I2C brightness control.
allOf:
- $ref: common.yaml#
properties:
compatible:
const: silergy,sy7758
reg:
maxItems: 1
vdd-supply: true
enable-gpios:
maxItems: 1
required:
- compatible
- reg
- enable-gpios
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
backlight@11 {
compatible = "silergy,sy7758";
reg = <0x11>;
vdd-supply = <&bl_vdd>;
enable-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
};
};

170
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@ -0,0 +1,170 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/backlight/ti,tps65217.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TPS65217 family of regulators
maintainers:
- Eduard Bostina <egbostina@gmail.com>
description:
The TPS65217 chip contains a boost converter and current sinks which can be
used to drive LEDs for use as backlights.
properties:
compatible:
const: ti,tps65217
reg:
maxItems: 1
description: I2C slave address
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells":
const: 1
ti,pmic-shutdown-controller:
type: boolean
description:
Set the PMIC to shutdown on PWR_EN toggle.
backlight:
type: object
additionalProperties: false
description:
Node for specifying WLED1 and WLED2 lines in TPS65217.
properties:
isel:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
description: |
Selection bit. Valid values:
1 - ISEL1 (low-level)
2 - ISEL2 (high-level)
fdim:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [100, 200, 500, 1000]
description:
PWM dimming frequency in Hz.
default-brightness:
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 100
required:
- isel
- fdim
- default-brightness
regulators:
type: object
additionalProperties: false
description:
List of child nodes that specify the regulator initialization data.
Not all regulators for the given device need to be present.
patternProperties:
"^(dcdc[1-3]|ldo[1-4])$":
type: object
$ref: /schemas/regulator/regulator.yaml#
unevaluatedProperties: false
charger:
$ref: /schemas/power/supply/tps65217-charger.yaml#
unevaluatedProperties: false
pwrbutton:
$ref: /schemas/input/ti,tps65217-pwrbutton.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic@24 {
compatible = "ti,tps65217";
reg = <0x24>;
interrupt-controller;
#interrupt-cells = <1>;
ti,pmic-shutdown-controller;
backlight {
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
default-brightness = <50>;
};
charger {
compatible = "ti,tps65217-charger";
interrupts = <0>, <1>;
interrupt-names = "USB", "AC";
};
pwrbutton {
compatible = "ti,tps65217-pwrbutton";
interrupts = <2>;
};
regulators {
dcdc1 {
regulator-name = "vdds_dpr";
regulator-always-on;
};
dcdc2 {
regulator-name = "vdd_mpu";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1351500>;
regulator-boot-on;
regulator-always-on;
};
dcdc3 {
regulator-name = "vdd_core";
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo1 {
regulator-name = "vio,vrtc,vdds";
regulator-always-on;
};
ldo2 {
regulator-name = "vdd_3v3aux";
regulator-always-on;
};
ldo3 {
regulator-name = "vdd_1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo4 {
regulator-name = "vdd_3v3a";
regulator-always-on;
};
};
};
};

27
Documentation/devicetree/bindings/leds/backlight/tps65217-backlight.txt
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@ -1,27 +0,0 @@
TPS65217 family of regulators
The TPS65217 chip contains a boost converter and current sinks which can be
used to drive LEDs for use as backlights.
Required properties:
- compatible: "ti,tps65217"
- reg: I2C slave address
- backlight: node for specifying WLED1 and WLED2 lines in TPS65217
- isel: selection bit, valid values: 1 for ISEL1 (low-level) and 2 for ISEL2 (high-level)
- fdim: PWM dimming frequency, valid values: 100, 200, 500, 1000
- default-brightness: valid values: 0-100
Each regulator is defined using the standard binding for regulators.
Example:
tps: tps@24 {
reg = <0x24>;
compatible = "ti,tps65217";
backlight {
isel = <1>; /* 1 - ISET1, 2 ISET2 */
fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
default-brightness = <50>;
};
};

96
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@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/brcm,bcm6358-leds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LEDs connected to Broadcom BCM6358 controller
description: |
This controller is present on BCM6358 and BCM6368.
In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller),
which can either be controlled by software (exporting the 74x164 as spi-gpio.
See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or
by hardware using this driver.
maintainers:
- Álvaro Fernández Rojas <noltari@gmail.com>
properties:
compatible:
const: brcm,bcm6358-leds
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
brcm,clk-div:
description: SCK signal divider.
default: 1
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
brcm,clk-dat-low:
description: Makes clock and data signals active low.
type: boolean
patternProperties:
"^led@1?[0-9a-f]$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
description: Each LED is represented as a sub-node of
this device.
properties:
reg:
description: LED pin number (0 to 31).
maxItems: 1
required:
- reg
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/leds/common.h>
led-controller@fffe00d0 {
compatible = "brcm,bcm6358-leds";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffe00d0 0x8>;
led@0 {
reg = <0>;
active-low;
label = "white:alarm";
};
led@2 {
reg = <2>;
active-low;
label = "white:tv";
};
led@3 {
reg = <3>;
active-low;
label = "white:tel";
};
led@4 {
reg = <4>;
active-low;
label = "white:adsl";
};
};
...

12
Documentation/devicetree/bindings/leds/common.yaml
View File

@ -73,6 +73,16 @@ properties:
- keep
default: off
default-intensity:
description:
The initial intensity of the LED color component. As the intensity of
each sub-LED is multiplied with the overall brightness, without this
property on a sub-LED, it may effectively be initialized at minimum
brightness regardless of its linux,default-trigger and default-brightness
properties.
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
linux,default-trigger:
description:
This parameter, if present, is a string defining the trigger assigned to
@ -106,6 +116,8 @@ properties:
- bluetooth-power
# LED indicates camera flash state
- flash
# LED indicates level of GPIO input referenced by trigger-sources
- gpio
# LED indicated keyboard capslock
- kbd-capslock
# LED indicates MTD memory activity

85
Documentation/devicetree/bindings/leds/lacie,ns2-leds.yaml Normal file
View File

@ -0,0 +1,85 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/leds/lacie,ns2-leds.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Dual-GPIO LEDs found on Network Space v2 (and parents)
maintainers:
- Simon Guinot <simon.guinot@sequanux.org>
description:
The Network Space v2 dual-GPIO LED is wired to a CPLD. Three different LED
modes are available, off, on and SATA activity blinking. The LED modes are
controlled through two GPIOs (command and slow), each combination of values
for the command/slow GPIOs corresponds to a LED mode.
properties:
compatible:
const: lacie,ns2-leds
additionalProperties:
type: object
$ref: common.yaml#
unevaluatedProperties: false
description: Each child node represents a single LED
properties:
cmd-gpio:
maxItems: 1
description: GPIO connected to the command LED output
slow-gpio:
maxItems: 1
description: GPIO connected to the slow LED output
num-modes:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of entries in modes-map.
modes-map:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
description:
A mapping between LED modes (off, on or SATA activity blinking) and
the corresponding cmd-gpio/slow-gpio values. All the GPIO values
combinations should be given in order to avoid having an unknown
mode at driver probe time.
items:
items:
- description: LED mode
enum: [0, 1, 2]
- description: Command GPIO level
enum: [0, 1]
- description: Slow GPIO level
enum: [0, 1]
required:
- cmd-gpio
- slow-gpio
- modes-map
required:
- compatible
examples:
- |
#include <dt-bindings/leds/leds-ns2.h>
led-controller {
compatible = "lacie,ns2-leds";
led-0 {
label = "ns2:blue:sata";
slow-gpio = <&gpio0 29 0>;
cmd-gpio = <&gpio0 30 0>;
modes-map = <NS_V2_LED_OFF 0 1
NS_V2_LED_ON 1 0
NS_V2_LED_ON 0 0
NS_V2_LED_SATA 1 1>;
};
};
...

143
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@ -1,143 +0,0 @@
LEDs connected to Broadcom BCM6358 controller
This controller is present on BCM6358 and BCM6368.
In these SoCs there are Serial LEDs (LEDs connected to a 74x164 controller),
which can either be controlled by software (exporting the 74x164 as spi-gpio.
See Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml), or
by hardware using this driver.
Required properties:
- compatible : should be "brcm,bcm6358-leds".
- #address-cells : must be 1.
- #size-cells : must be 0.
- reg : BCM6358 LED controller address and size.
Optional properties:
- brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
Default : 1
- brcm,clk-dat-low : Boolean, makes clock and data signals active low.
Default : false
Each LED is represented as a sub-node of the brcm,bcm6358-leds device.
LED sub-node required properties:
- reg : LED pin number (only LEDs 0 to 31 are valid).
LED sub-node optional properties:
- label : see Documentation/devicetree/bindings/leds/common.txt
- default-state : see
Documentation/devicetree/bindings/leds/common.txt
- linux,default-trigger : see
Documentation/devicetree/bindings/leds/common.txt
Examples:
Scenario 1 : BCM6358
leds0: led-controller@fffe00d0 {
compatible = "brcm,bcm6358-leds";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xfffe00d0 0x8>;
alarm_white {
reg = <0>;
active-low;
label = "white:alarm";
};
tv_white {
reg = <2>;
active-low;
label = "white:tv";
};
tel_white {
reg = <3>;
active-low;
label = "white:tel";
};
adsl_white {
reg = <4>;
active-low;
label = "white:adsl";
};
};
Scenario 2 : BCM6368
leds0: led-controller@100000d0 {
compatible = "brcm,bcm6358-leds";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x100000d0 0x8>;
brcm,pol-low;
brcm,clk-div = <4>;
power_red {
reg = <0>;
active-low;
label = "red:power";
};
power_green {
reg = <1>;
active-low;
label = "green:power";
default-state = "on";
};
power_blue {
reg = <2>;
label = "blue:power";
};
broadband_red {
reg = <3>;
active-low;
label = "red:broadband";
};
broadband_green {
reg = <4>;
label = "green:broadband";
};
broadband_blue {
reg = <5>;
active-low;
label = "blue:broadband";
};
wireless_red {
reg = <6>;
active-low;
label = "red:wireless";
};
wireless_green {
reg = <7>;
active-low;
label = "green:wireless";
};
wireless_blue {
reg = <8>;
label = "blue:wireless";
};
phone_red {
reg = <9>;
active-low;
label = "red:phone";
};
phone_green {
reg = <10>;
active-low;
label = "green:phone";
};
phone_blue {
reg = <11>;
label = "blue:phone";
};
upgrading_red {
reg = <12>;
active-low;
label = "red:upgrading";
};
upgrading_green {
reg = <13>;
active-low;
label = "green:upgrading";
};
upgrading_blue {
reg = <14>;
label = "blue:upgrading";
};
};

35
Documentation/devicetree/bindings/leds/leds-ns2.txt
View File

@ -1,35 +0,0 @@
Binding for dual-GPIO LED found on Network Space v2 (and parents).
Required properties:
- compatible: "lacie,ns2-leds".
Each LED is represented as a sub-node of the ns2-leds device.
Required sub-node properties:
- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification.
- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification.
- modes-map: A mapping between LED modes (off, on or SATA activity blinking) and
the corresponding cmd-gpio/slow-gpio values. All the GPIO values combinations
should be given in order to avoid having an unknown mode at driver probe time.
Optional sub-node properties:
- label: Name for this LED. If omitted, the label is taken from the node name.
- linux,default-trigger: Trigger assigned to the LED.
Example:
#include <dt-bindings/leds/leds-ns2.h>
ns2-leds {
compatible = "lacie,ns2-leds";
blue-sata {
label = "ns2:blue:sata";
slow-gpio = <&gpio0 29 0>;
cmd-gpio = <&gpio0 30 0>;
modes-map = <NS_V2_LED_OFF 0 1
NS_V2_LED_ON 1 0
NS_V2_LED_ON 0 0
NS_V2_LED_SATA 1 1>;
};
};

4
Documentation/devicetree/bindings/leds/leds-pwm-multicolor.yaml
View File

@ -45,6 +45,8 @@ properties:
color: true
default-intensity: true
required:
- pwms
- color
@ -63,12 +65,14 @@ examples:
multi-led {
color = <LED_COLOR_ID_RGB>;
linux,default-trigger = "default-on";
function = LED_FUNCTION_INDICATOR;
max-brightness = <65535>;
led-red {
pwms = <&pwm1 0 1000000>;
color = <LED_COLOR_ID_RED>;
default-intensity = <65535>;
};
led-green {

108
Documentation/devicetree/bindings/leds/nxp,pca963x.yaml
View File

@ -62,18 +62,52 @@ properties:
open-drain, newer chips to totem pole).
patternProperties:
"^led@[0-9a-f]+$":
"^led@[0-9a-f]$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
properties:
reg:
minimum: 0
maximum: 15
required:
- reg
"^multi-led@[0-9a-f]$":
type: object
$ref: leds-class-multicolor.yaml#
unevaluatedProperties: false
properties:
reg:
maximum: 15
"#address-cells":
const: 1
"#size-cells":
const: 0
patternProperties:
"^led@[0-9a-f]$":
type: object
$ref: common.yaml#
unevaluatedProperties: false
properties:
reg:
maximum: 15
required:
- reg
- color
required:
- reg
- "#address-cells"
- "#size-cells"
allOf:
- if:
properties:
@ -84,16 +118,34 @@ allOf:
- nxp,pca9633
then:
patternProperties:
"^led@[0-9a-f]+$":
"^.*led@[0-9a-f]$":
properties:
reg:
maximum: 3
else:
"^multi-led@[0-9a-f]$":
patternProperties:
"^led@[0-9a-f]$":
properties:
reg:
maximum: 3
- if:
properties:
compatible:
contains:
enum:
- nxp,pca9634
then:
patternProperties:
"^led@[0-9a-f]+$":
"^.*led@[0-9a-f]$":
properties:
reg:
maximum: 7
"^multi-led@[0-9a-f]$":
patternProperties:
"^led@[0-9a-f]$":
properties:
reg:
maximum: 7
additionalProperties: false
@ -137,4 +189,50 @@ examples:
};
};
- |
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
led-controller@62 {
compatible = "nxp,pca9633";
reg = <0x62>;
#address-cells = <1>;
#size-cells = <0>;
/* Three channels controlling one RGB LED */
multi-led@0 {
reg = <0>;
color = <LED_COLOR_ID_RGB>;
function = LED_FUNCTION_STATUS;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
};
};
/* Remaining channel used as a plain white LED */
led@3 {
reg = <3>;
color = <LED_COLOR_ID_WHITE>;
function = LED_FUNCTION_STATUS;
};
};
};
...

2
Documentation/devicetree/bindings/mfd/marvell,88pm886-a1.yaml
View File

@ -29,7 +29,7 @@ properties:
type: object
additionalProperties: false
patternProperties:
"^(ldo(1[0-6]|[1-9])|buck[1-5])$":
"^(ldo(1[0-6]|[1-9])|buck[1-5]|vbus)$":
type: object
$ref: /schemas/regulator/regulator.yaml#
description: LDO or buck regulator.

1
Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
View File

@ -26,6 +26,7 @@ properties:
- mediatek,mt8183-scpsys
- mediatek,mt8186-scpsys
- mediatek,mt8188-scpsys
- mediatek,mt8189-scpsys
- mediatek,mt8192-scpsys
- mediatek,mt8195-scpsys
- mediatek,mt8365-scpsys

27
Documentation/devicetree/bindings/mfd/omap-usb-tll.txt
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@ -1,27 +0,0 @@
OMAP HS USB Host TLL (Transceiver-Less Interface)
Required properties:
- compatible : should be "ti,usbhs-tll"
- reg : should contain one register range i.e. start and length
- interrupts : should contain the TLL module's interrupt
- ti,hwmod : must contain "usb_tll_hs"
Optional properties:
- clocks: a list of phandles and clock-specifier pairs, one for each entry in
clock-names.
- clock-names: should include:
* "usb_tll_hs_usb_ch0_clk" - USB TLL channel 0 clock
* "usb_tll_hs_usb_ch1_clk" - USB TLL channel 1 clock
* "usb_tll_hs_usb_ch2_clk" - USB TLL channel 2 clock
Example:
usbhstll: usbhstll@4a062000 {
compatible = "ti,usbhs-tll";
reg = <0x4a062000 0x1000>;
interrupts = <78>;
ti,hwmods = "usb_tll_hs";
};

9
Documentation/devicetree/bindings/mfd/qcom,spmi-pmic.yaml
View File

@ -80,6 +80,7 @@ properties:
- qcom,pmcx0102
- qcom,pmd8028
- qcom,pmd9635
- qcom,pmg1110
- qcom,pmh0101
- qcom,pmh0104
- qcom,pmh0110
@ -165,6 +166,10 @@ patternProperties:
type: object
$ref: /schemas/pinctrl/qcom,pmic-gpio.yaml#
"^haptics@[0-9a-f]+$":
type: object
$ref: /schemas/input/qcom,spmi-haptics.yaml#
"^led-controller@[0-9a-f]+$":
type: object
$ref: /schemas/leds/qcom,spmi-flash-led.yaml#
@ -193,6 +198,10 @@ patternProperties:
type: object
$ref: /schemas/thermal/qcom,spmi-temp-alarm.yaml#
"^temperature-sensor@[0-9a-f]+$":
type: object
$ref: /schemas/thermal/qcom,pm8775-mbg-tm.yaml#
"^typec@[0-9a-f]+$":
type: object
$ref: /schemas/usb/qcom,pmic-typec.yaml#

4
Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml
View File

@ -17,6 +17,8 @@ properties:
compatible:
items:
- enum:
- qcom,hawi-tcsr
- qcom,maili-tcsr
- qcom,msm8976-tcsr
- qcom,msm8998-tcsr
- qcom,nord-tcsr
@ -34,6 +36,7 @@ properties:
- qcom,sdx55-tcsr
- qcom,sdx65-tcsr
- qcom,sdx75-tcsr
- qcom,shikra-tcsr
- qcom,sm4450-tcsr
- qcom,sm6115-tcsr
- qcom,sm8150-tcsr
@ -50,6 +53,7 @@ properties:
- qcom,tcsr-ipq8064
- qcom,tcsr-ipq8074
- qcom,tcsr-ipq9574
- qcom,tcsr-ipq9650
- qcom,tcsr-mdm9615
- qcom,tcsr-msm8226
- qcom,tcsr-msm8660

2
Documentation/devicetree/bindings/mfd/st,stmpe.yaml
View File

@ -20,7 +20,7 @@ allOf:
properties:
compatible:
enum:
- st,stmpe601
- st,stmpe610
- st,stmpe801
- st,stmpe811
- st,stmpe1600

34
Documentation/devicetree/bindings/mfd/syscon-common.yaml
View File

@ -32,6 +32,7 @@ properties:
compatible:
contains:
const: syscon
# Always require a specific compatible for syscon
minItems: 2
maxItems: 5 # Should be enough
@ -52,11 +53,44 @@ allOf:
contains:
const: simple-mfd
then:
# Always require a specific compatible for syscon with simple-mfd
properties:
compatible:
minItems: 3
maxItems: 5
- if:
properties:
compatible:
contains:
const: simple-bus
then:
# simple-bus conflicts with syscon - if a device is a system controller
# with miscellaneous registers, then it has at least one dedicated
# function thus it is not a simple bus. Allow existing exceptions.
if:
properties:
compatible:
not:
contains:
# This list CANNOT grow
enum:
- cznic,turris1x-cpld
- img,pistachio-cr-periph
- ti,am3352-scm-conf
- ti,am4372-scm-conf
- ti,dm814-scm-conf
- ti,dm8168-scm-conf
- ti,dra7-scm-conf
- ti,omap2-scm-conf
- ti,omap3-scm-conf
- ti,omap4-sysc-padconf-global
- ti,omap5-scm-wkup-conf
- ti,omap5-sysc-padconf-global
then:
required:
- incorrect-usage-of-simple-bus-and-syscon
additionalProperties: true
examples:

118
Documentation/devicetree/bindings/mfd/syscon.yaml
View File

@ -19,122 +19,6 @@ description: |
maintainers:
- Lee Jones <lee@kernel.org>
# Need a select with all compatibles listed for compatibility with older
# dtschema (<2024.02), so this will not be selected for other schemas having
# syscon fallback.
select:
properties:
compatible:
contains:
enum:
- airoha,en7581-pbus-csr
- al,alpine-sysfabric-service
- allwinner,sun8i-a83t-system-controller
- allwinner,sun8i-h3-system-controller
- allwinner,sun8i-v3s-system-controller
- allwinner,sun50i-a64-system-controller
- altr,l3regs
- altr,sdr-ctl
- amd,pensando-elba-syscon
- amlogic,meson-mx-assist
- amlogic,meson-mx-bootrom
- amlogic,meson8-analog-top
- amlogic,meson8b-analog-top
- amlogic,meson8-pmu
- amlogic,meson8b-pmu
- apm,merlin-poweroff-mailbox
- apm,mustang-poweroff-mailbox
- apm,xgene-csw
- apm,xgene-efuse
- apm,xgene-mcb
- apm,xgene-rb
- apm,xgene-scu
- atmel,sama5d2-sfrbu
- atmel,sama5d3-nfc-io
- atmel,sama5d3-sfrbu
- atmel,sama5d4-sfrbu
- axis,artpec6-syscon
- brcm,cru-clkset
- brcm,sr-cdru
- brcm,sr-mhb
- cirrus,ep7209-syscon1
- cirrus,ep7209-syscon2
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
- econet,en751221-chip-scu
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
- fsl,ls1088a-reset
- fsl,vf610-anatop
- fsl,vf610-mscm-cpucfg
- hisilicon,dsa-subctrl
- hisilicon,hi6220-sramctrl
- hisilicon,hip04-ppe
- hisilicon,pcie-sas-subctrl
- hisilicon,peri-subctrl
- hpe,gxp-sysreg
- loongson,ls1b-syscon
- loongson,ls1c-syscon
- lsi,axxia-syscon
- marvell,armada-3700-cpu-misc
- marvell,armada-3700-nb-pm
- marvell,armada-3700-avs
- marvell,armada-3700-usb2-host-device-misc
- marvell,armada-3700-usb2-host-misc
- marvell,dove-global-config
- mediatek,mt2701-pctl-a-syscfg
- mediatek,mt2712-pctl-a-syscfg
- mediatek,mt6397-pctl-pmic-syscfg
- mediatek,mt7981-topmisc
- mediatek,mt7988-topmisc
- mediatek,mt8135-pctl-a-syscfg
- mediatek,mt8135-pctl-b-syscfg
- mediatek,mt8173-pctl-a-syscfg
- mediatek,mt8365-syscfg
- microchip,lan966x-cpu-syscon
- microchip,mpfs-control-scb
- microchip,mpfs-sysreg-scb
- microchip,sam9x60-sfr
- microchip,sama7d65-ddr3phy
- microchip,sama7d65-sfrbu
- microchip,sama7g5-ddr3phy
- mscc,ocelot-cpu-syscon
- mstar,msc313-pmsleep
- nuvoton,ma35d1-sys
- nuvoton,wpcm450-shm
- nxp,s32g2-gpr
- nxp,s32g3-gpr
- qcom,apq8064-mmss-sfpb
- qcom,apq8064-sps-sic
- rockchip,px30-qos
- rockchip,rk3036-qos
- rockchip,rk3066-qos
- rockchip,rk3128-qos
- rockchip,rk3228-qos
- rockchip,rk3288-qos
- rockchip,rk3368-qos
- rockchip,rk3399-qos
- rockchip,rk3528-qos
- rockchip,rk3562-qos
- rockchip,rk3568-qos
- rockchip,rk3576-qos
- rockchip,rk3588-qos
- rockchip,rv1126-qos
- st,spear1340-misc
- stericsson,nomadik-pmu
- starfive,jh7100-sysmain
- ti,am62-opp-efuse-table
- ti,am62-usb-phy-ctrl
- ti,am625-dss-oldi-io-ctrl
- ti,am62p-cpsw-mac-efuse
- ti,am654-dss-oldi-io-ctrl
- ti,j784s4-acspcie-proxy-ctrl
- ti,j784s4-pcie-ctrl
- ti,keystone-pllctrl
required:
- compatible
properties:
compatible:
oneOf:
@ -175,6 +59,7 @@ properties:
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
- econet,en751221-chip-scu
- eswin,eic7700-syscfg
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
@ -189,6 +74,7 @@ properties:
- hpe,gxp-sysreg
- loongson,ls1b-syscon
- loongson,ls1c-syscon
- loongson,ls2k0300-chipid-syscon
- lsi,axxia-syscon
- marvell,armada-3700-cpu-misc
- marvell,armada-3700-nb-pm

53
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@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/ti,usbhs-tll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OMAP HS USB Host TLL (Transceiver-Less Interface)
maintainers:
- Eduard Bostina <egbostina@gmail.com>
properties:
compatible:
const: ti,usbhs-tll
reg:
maxItems: 1
interrupts:
maxItems: 1
ti,hwmods:
description: Name of the hwmod associated with the USB TLL.
$ref: /schemas/types.yaml#/definitions/string
const: usb_tll_hs
clocks:
minItems: 1
maxItems: 3
description: A list of phandles and clock-specifier pairs.
clock-names:
minItems: 1
items:
- const: usb_tll_hs_usb_ch0_clk
- const: usb_tll_hs_usb_ch1_clk
- const: usb_tll_hs_usb_ch2_clk
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
usb-tll@4a062000 {
compatible = "ti,usbhs-tll";
reg = <0x4a062000 0x1000>;
interrupts = <78>;
ti,hwmods = "usb_tll_hs";
};

78
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@ -1,78 +0,0 @@
TPS65217 family of regulators
Required properties:
- compatible: "ti,tps65217"
- reg: I2C slave address
- regulators: list of regulators provided by this controller, must be named
after their hardware counterparts: dcdc[1-3] and ldo[1-4]
- regulators: This is the list of child nodes that specify the regulator
initialization data for defined regulators. Not all regulators for the given
device need to be present. The definition for each of these nodes is defined
using the standard binding for regulators found at
Documentation/devicetree/bindings/regulator/regulator.txt.
Optional properties:
- ti,pmic-shutdown-controller: Telling the PMIC to shutdown on PWR_EN toggle.
The valid names for regulators are:
tps65217: dcdc1, dcdc2, dcdc3, ldo1, ldo2, ldo3 and ldo4
Each regulator is defined using the standard binding for regulators.
Example:
tps: tps@24 {
compatible = "ti,tps65217";
ti,pmic-shutdown-controller;
regulators {
dcdc1_reg: dcdc1 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
dcdc2_reg: dcdc2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
dcdc3_reg: dcc3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: ldo1 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: ldo2 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: ldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: ldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};

2
Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt
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@ -75,7 +75,7 @@ SoCs only:
- clocks: Should contain the device's input clock, and should be
defined as per the bindings in,
Documentation/devicetree/bindings/clock/keystone-gate.txt
Documentation/devicetree/bindings/clock/ti,keystone,psc-clock.yaml
The following are mandatory properties for Keystone 2 66AK2G SoCs only:

42
Documentation/devicetree/bindings/reset/qcom,shikra-audiocore-csr.yaml Normal file
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@ -0,0 +1,42 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/reset/qcom,shikra-audiocore-csr.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Audio Core CSR for Qualcomm Shikra SoC
maintainers:
- Imran Shaik <imran.shaik@oss.qualcomm.com>
description: |
Audio Core CSR module provides the resets on Qualcomm Shikra SoC platform.
See also:
- include/dt-bindings/clock/qcom,shikra-audiocorecc.h
properties:
compatible:
const: qcom,shikra-audiocore-csr
reg:
maxItems: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
- '#reset-cells'
additionalProperties: false
examples:
- |
reset-controller@a0b4000 {
compatible = "qcom,shikra-audiocore-csr";
reg = <0x0a0b4000 0x1000>;
#reset-cells = <1>;
};
...

13
Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
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@ -33,6 +33,7 @@ properties:
- enum:
- allwinner,sun20i-d1-rtc
- allwinner,sun55i-a523-rtc
- allwinner,sun60i-a733-rtc
- const: allwinner,sun50i-r329-rtc
reg:
@ -175,6 +176,18 @@ allOf:
interrupts:
minItems: 2
- if:
properties:
compatible:
contains:
enum:
- allwinner,sun50i-h616-rtc
- allwinner,sun50i-r329-rtc
then:
properties:
clock-output-names: false
required:
- "#clock-cells"
- compatible

21
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@ -1,21 +0,0 @@
* Microchip PIC32 Real Time Clock and Calendar
The RTCC keeps time in hours, minutes, and seconds, and one half second. It
provides a calendar in weekday, date, month, and year. It also provides a
configurable alarm.
Required properties:
- compatible: should be: "microchip,pic32mzda-rtc"
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: RTC alarm/event interrupt
- clocks: clock phandle
Example:
rtc: rtc@1f8c0000 {
compatible = "microchip,pic32mzda-rtc";
reg = <0x1f8c0000 0x60>;
interrupts = <166 IRQ_TYPE_EDGE_RISING>;
clocks = <&PBCLK6>;
};

50
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@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/microchip,pic32mzda-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIC32 Real Time Clock and Calendar
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
description: |
The Microchip PIC32 Real Time Clock and Calendar (RTCC) keeps time in hours,
minutes, seconds, and one half second. It also provides a calendar with
weekday, date, month, and year, along with a configurable alarm.
allOf:
- $ref: rtc.yaml#
properties:
compatible:
const: microchip,pic32mzda-rtc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
- clocks
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
rtc@1f8c0000 {
compatible = "microchip,pic32mzda-rtc";
reg = <0x1f8c0000 0x60>;
interrupts = <166 IRQ_TYPE_EDGE_RISING>;
clocks = <&PBCLK6>;
};

35
Documentation/devicetree/bindings/rtc/renesas,rzn1-rtc.yaml
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@ -9,15 +9,19 @@ title: Renesas RZ/N1 SoCs Real-Time Clock
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
allOf:
- $ref: rtc.yaml#
properties:
compatible:
items:
- enum:
- renesas,r9a06g032-rtc
- const: renesas,rzn1-rtc
oneOf:
- items:
- enum:
- renesas,r9a06g032-rtc
- const: renesas,rzn1-rtc
- const: renesas,r9a09g077-rtc
- items:
- const: renesas,r9a09g087-rtc
- const: renesas,r9a09g077-rtc
reg:
maxItems: 1
@ -54,6 +58,23 @@ required:
- clock-names
- power-domains
allOf:
- $ref: rtc.yaml#
- if:
properties:
compatible:
contains:
enum:
- renesas,r9a09g077-rtc
- renesas,r9a09g087-rtc
then:
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
unevaluatedProperties: false
examples:

27
Documentation/devicetree/bindings/rtc/rtc-cmos.txt
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@ -1,27 +0,0 @@
Motorola mc146818 compatible RTC
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Required properties:
- compatible : "motorola,mc146818"
- reg : should contain registers location and length.
Optional properties:
- interrupts : should contain interrupt.
- ctrl-reg : Contains the initial value of the control register also
called "Register B".
- freq-reg : Contains the initial value of the frequency register also
called "Register A".
"Register A" and "B" are usually initialized by the firmware (BIOS for
instance). If this is not done, it can be performed by the driver.
ISA Example:
rtc@70 {
compatible = "motorola,mc146818";
interrupts = <8 3>;
interrupt-parent = <&ioapic1>;
ctrl-reg = <2>;
freq-reg = <0x26>;
reg = <1 0x70 2>;
};

63
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@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/rtc-cmos.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Motorola mc146818 compatible RTC
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
properties:
compatible:
oneOf:
- const: motorola,mc146818
- items:
- const: intel,ce4100-rtc
- const: motorola,mc146818
reg:
maxItems: 1
interrupts:
maxItems: 1
ctrl-reg:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Initial value of the control register
(also known as Register B).
freq-reg:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Initial value of the frequency register
(also known as Register A).
required:
- compatible
- reg
allOf:
- $ref: rtc.yaml#
unevaluatedProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <1>;
rtc@1,70 {
compatible = "motorola,mc146818";
reg = <0x1 0x70 0x2>;
interrupts = <8 3>;
ctrl-reg = <2>;
freq-reg = <0x26>;
};
};

53
Documentation/devicetree/bindings/rtc/rtc-omap.txt
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@ -1,53 +0,0 @@
TI Real Time Clock
Required properties:
- compatible:
- "ti,da830-rtc" - for RTC IP used similar to that on DA8xx SoC family.
- "ti,am3352-rtc" - for RTC IP used similar to that on AM335x SoC family.
This RTC IP has special WAKE-EN Register to enable
Wakeup generation for event Alarm. It can also be
used to control an external PMIC via the
pmic_power_en pin.
- "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
- reg: Address range of rtc register set
- interrupts: rtc timer, alarm interrupts in order
Optional properties:
- system-power-controller: whether the rtc is controlling the system power
through pmic_power_en
- clocks: Any internal or external clocks feeding in to rtc
- clock-names: Corresponding names of the clocks
- pinctrl-0: a phandle pointing to the pin settings for the device
- pinctrl-names: should be "default"
Optional subnodes:
- generic pinctrl node
Required pinctrl subnodes properties:
- pins - Names of ext_wakeup pins to configure
Optional pinctrl subnodes properties:
- input-enable - Enables ext_wakeup
- ti,active-high - Set input active high (by default active low)
Example:
rtc@1c23000 {
compatible = "ti,da830-rtc";
reg = <0x23000 0x1000>;
interrupts = <19
19>;
interrupt-parent = <&intc>;
system-power-controller;
clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
clock-names = "ext-clk", "int-clk";
pinctrl-0 = <&ext_wakeup>;
pinctrl-names = "default";
ext_wakeup: ext-wakeup {
pins = "ext_wakeup0";
input-enable;
ti,active-high;
};
};

32
Documentation/devicetree/bindings/rtc/rtc-palmas.txt
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@ -1,32 +0,0 @@
Palmas RTC controller bindings
Required properties:
- compatible:
- "ti,palmas-rtc" for palma series of the RTC controller
- interrupts: Interrupt number of RTC submodule on device.
Optional properties:
- ti,backup-battery-chargeable: The Palmas series device like TPS65913 or
TPS80036 supports the backup battery for powering the RTC when main
battery is removed or in very low power state. The backup battery
can be chargeable or non-chargeable. This flag will tells whether
battery is chargeable or not. If charging battery then driver can
enable the charging.
- ti,backup-battery-charge-high-current: Enable high current charging in
backup battery. Device supports the < 100uA and > 100uA charging.
The high current will be > 100uA. Absence of this property will
charge battery to lower current i.e. < 100uA.
Example:
palmas: tps65913@58 {
...
palmas_rtc: rtc {
compatible = "ti,palmas-rtc";
interrupt-parent = <&palmas>;
interrupts = <8 0>;
ti,backup-battery-chargeable;
ti,backup-battery-charge-high-current;
};
...
};

140
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@ -0,0 +1,140 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ti,omap-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments OMAP Real Time Clock
maintainers:
- Keerthy <j-keerthy@ti.com>
- Afzal Mohammed <afzal@ti.com>
description:
The OMAP RTC is a year/month/day/hours/minutes/seconds BCD clock with
century-range alarm matching, driven by the 32kHz clock.
properties:
compatible:
oneOf:
- const: ti,da830-rtc
- items:
- const: ti,am3352-rtc
- const: ti,da830-rtc
- items:
- const: ti,am4372-rtc
- const: ti,am3352-rtc
- const: ti,da830-rtc
reg:
maxItems: 1
interrupts:
minItems: 2
maxItems: 2
system-power-controller:
type: boolean
description:
Indicates that this RTC controls system power via the pmic_power_en pin.
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- enum: [ext-clk, int-clk]
- const: int-clk
pinctrl-0:
description:
Phandle to pin configuration for the external wakeup pins.
pinctrl-names:
minItems: 1
ti,hwmods:
$ref: /schemas/types.yaml#/definitions/string
description:
Name of the hwmod associated with the RTC.
const: rtc
deprecated: true
patternProperties:
"^ext-wakeup(-[0-9]+)?$":
type: object
description:
Child node describing external wakeup pin configuration.
properties:
pins:
pattern: '^ext_wakeup[0-3]$'
input-enable:
type: boolean
description:
Enables the external wakeup input on the selected pin.
ti,active-high:
type: boolean
description:
Sets the wakeup input polarity to active high. By default the
input is active low.
required:
- pins
additionalProperties: false
required:
- compatible
- reg
- interrupts
allOf:
- $ref: rtc.yaml#
- if:
not:
properties:
compatible:
contains:
const: ti,am3352-rtc
then:
properties:
system-power-controller: false
patternProperties:
"^ext-wakeup(-[0-9]+)?$": false
unevaluatedProperties: false
examples:
- |
rtc@23000 {
compatible = "ti,da830-rtc";
reg = <0x23000 0x1000>;
interrupts = <19>, <19>;
clocks = <&clk_32768_ck>;
clock-names = "int-clk";
};
- |
rtc@0 {
compatible = "ti,am3352-rtc", "ti,da830-rtc";
reg = <0x0 0x1000>;
interrupts = <75>, <76>;
system-power-controller;
clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
clock-names = "ext-clk", "int-clk";
pinctrl-0 = <&ext_wakeup>;
pinctrl-names = "default";
ext-wakeup {
pins = "ext_wakeup0";
input-enable;
ti,active-high;
};
};

57
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@ -0,0 +1,57 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/rtc/ti,palmas-rtc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments Palmas RTC
maintainers:
- Eduard Bostina <egbostina@gmail.com>
allOf:
- $ref: /schemas/rtc/rtc.yaml#
properties:
compatible:
const: ti,palmas-rtc
interrupts:
maxItems: 1
wakeup-source: true
ti,backup-battery-chargeable:
type: boolean
description:
The backup battery can be chargeable or non-chargeable. This flag
indicates whether the battery is chargeable. If present, the driver
can enable charging.
ti,backup-battery-charge-high-current:
type: boolean
description:
Enable high current charging in the backup battery.
Device supports the < 100uA and > 100uA charging. The high current will
be > 100uA. Absence of this property will charge battery to lower
current i.e. < 100uA.
required:
- compatible
- interrupts
unevaluatedProperties: false
examples:
- |
pmic {
#address-cells = <1>;
#size-cells = <0>;
rtc {
compatible = "ti,palmas-rtc";
interrupts = <8 0>;
ti,backup-battery-chargeable;
ti,backup-battery-charge-high-current;
};
};

92
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@ -0,0 +1,92 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/cix/cix,sky1-audss-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cix Sky1 audio subsystem clock and reset unit
maintainers:
- Joakim Zhang <joakim.zhang@cixtech.com>
description: |
The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups
audio-related clock muxing, gating and block-level software reset control
in a single register block.
A single device node exposes both the clock controller and software reset
lines. The clock driver registers as a platform driver; the reset controller
is registered by an auxiliary driver bound from the clock driver.
Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS
clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are
defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.
Block-level software reset indices are exposed via #reset-cells; indices
are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.
The SoC syscon NoC (or bus) reset is described via resets. The audio
subsystem power domain is described via power-domains.
properties:
compatible:
const: cix,sky1-audss-cru
reg:
maxItems: 1
'#clock-cells':
const: 1
description:
Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h.
'#reset-cells':
const: 1
description:
Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h.
clocks:
items:
- description: I2S parent clock for sampling rates multiple of 8kHz.
- description: I2S parent clock for sampling rates multiple of 11.025kHz.
- description: Clock feeding most devices in AUDSS (NOC, DSP, SRAM, HDA, DMAC, I2S, and mailbox).
- description: Clock feeding HDA, timer and watchdog, which is a dedicated 48 MHz clock.
clock-names:
items:
- const: x8k
- const: x11k
- const: sys
- const: 48m
power-domains:
maxItems: 1
resets:
maxItems: 1
required:
- compatible
- reg
- '#clock-cells'
- '#reset-cells'
- clocks
- clock-names
- power-domains
- resets
additionalProperties: false
examples:
- |
audss_cru: clock-controller@7110000 {
compatible = "cix,sky1-audss-cru";
reg = <0x7110000 0x10000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&scmi_clk 76>, <&scmi_clk 78>,
<&scmi_clk 70>, <&scmi_clk 71>;
clock-names = "x8k", "x11k", "sys", "48m";
power-domains = <&smc_devpd 0>;
resets = <&s5_syscon 31>;
};

192
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@ -0,0 +1,192 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq7h-olb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mobileye EyeQ7H SoC system controller
maintainers:
- Benoît Monin <benoit.monin@bootlin.com>
- Grégory Clement <gregory.clement@bootlin.com>
- Théo Lebrun <theo.lebrun@bootlin.com>
- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
description:
OLB ("Other Logic Block") is a hardware system controller grouping
smaller blocks. Clocks and resets are generated by those blocks and
used by internal controllers of the SoC. The EyeQ7H SoC hosts 14
different OLB.
properties:
compatible:
items:
- enum:
- mobileye,eyeq7h-acc0-olb
- mobileye,eyeq7h-acc1-olb
- mobileye,eyeq7h-ddr0-olb
- mobileye,eyeq7h-ddr1-olb
- mobileye,eyeq7h-east-olb
- mobileye,eyeq7h-mips0-olb
- mobileye,eyeq7h-mips1-olb
- mobileye,eyeq7h-mips2-olb
- mobileye,eyeq7h-periph-east-olb
- mobileye,eyeq7h-periph-west-olb
- mobileye,eyeq7h-south-olb
- mobileye,eyeq7h-west-olb
- mobileye,eyeq7h-xnn0-olb
- mobileye,eyeq7h-xnn1-olb
- const: syscon
reg:
maxItems: 1
'#reset-cells':
description:
First cell is domain and optional if compatible has a single reset domain.
Second cell is reset index inside that domain.
enum: [ 1, 2 ]
'#clock-cells':
const: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
required:
- compatible
- reg
- '#clock-cells'
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-ddr0-olb
- mobileye,eyeq7h-ddr1-olb
- mobileye,eyeq7h-mips0-olb
- mobileye,eyeq7h-mips1-olb
- mobileye,eyeq7h-mips2-olb
- mobileye,eyeq7h-periph-east-olb
- mobileye,eyeq7h-south-olb
then:
properties:
clocks:
items:
- description: Reference input clock.
clock-names:
items:
- const: ref
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-east-olb
- mobileye,eyeq7h-west-olb
then:
properties:
clocks:
items:
- description: Reference input clock from the main oscillator.
- description: 100MHz reference input clock.
clock-names:
items:
- const: ref
- const: ref_100p0
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-acc0-olb
- mobileye,eyeq7h-acc1-olb
- mobileye,eyeq7h-periph-west-olb
- mobileye,eyeq7h-xnn0-olb
- mobileye,eyeq7h-xnn1-olb
then:
properties:
clocks:
items:
- description: 100MHz reference input clock.
- description: 106.6MHz reference input clock.
clock-names:
items:
- const: ref_100p0
- const: ref_106p6
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-ddr0-olb
- mobileye,eyeq7h-ddr1-olb
- mobileye,eyeq7h-east-olb
- mobileye,eyeq7h-periph-east-olb
- mobileye,eyeq7h-periph-west-olb
- mobileye,eyeq7h-west-olb
then:
properties:
'#reset-cells':
const: 1
required:
- '#reset-cells'
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-acc0-olb
- mobileye,eyeq7h-acc1-olb
- mobileye,eyeq7h-south-olb
- mobileye,eyeq7h-xnn0-olb
- mobileye,eyeq7h-xnn1-olb
then:
properties:
'#reset-cells':
const: 2
required:
- '#reset-cells'
- if:
properties:
compatible:
contains:
enum:
- mobileye,eyeq7h-mips0-olb
- mobileye,eyeq7h-mips1-olb
- mobileye,eyeq7h-mips2-olb
then:
properties:
'#reset-cells': false
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
system-controller0@45000000 {
compatible = "mobileye,eyeq7h-acc0-olb", "syscon";
reg = <0x0 0x45000000 0x0 0x1000>;
#reset-cells = <2>;
#clock-cells = <1>;
clocks = <&olb_south 7>, <&olb_east 5>;
clock-names = "ref_100p0", "ref_106p6";
};
};

13
Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
View File

@ -94,12 +94,23 @@ allOf:
nvmem-cell-names:
minItems: 2
- if:
properties:
compatible:
not:
contains:
enum:
- mediatek,mt8196-lvts-ap
- mediatek,mt8196-lvts-mcu
then:
required:
- resets
required:
- compatible
- reg
- interrupts
- clocks
- resets
- nvmem-cells
- nvmem-cell-names

72
Documentation/devicetree/bindings/thermal/qcom,pm8775-mbg-tm.yaml Normal file
View File

@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/qcom,pm8775-mbg-tm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm's SPMI PMIC MBG Thermal Monitoring
maintainers:
- Jishnu Prakash <jishnu.prakash@oss.qualcomm.com>
- Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
description:
Qualcomm's MBG(Master Bandgap) temperature alarm monitors the die
temperature and generates an interrupt if the PMIC die temperature is
over a set of programmable temperature thresholds. It allows monitoring
for both hot and cold, LVL1 and LVL2 thresholds, which makes it different
from the existing temp alarm peripheral. The interrupt comes over SPMI
and the MBG's fault status register gives details to understand whether
it is a hot/cold and LVL1/LVL2 violation.
properties:
compatible:
const: qcom,pm8775-mbg-tm
reg:
maxItems: 1
interrupts:
maxItems: 1
io-channels:
items:
- description: ADC channel, which reports chip die temperature.
io-channel-names:
items:
- const: thermal
'#thermal-sensor-cells':
const: 0
required:
- compatible
- reg
- interrupts
- io-channels
- io-channel-names
allOf:
- $ref: thermal-sensor.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
#address-cells = <1>;
#size-cells = <0>;
temperature-sensor@d700 {
compatible = "qcom,pm8775-mbg-tm";
reg = <0xd700>;
interrupts = <0x1 0xd7 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8775_adc 0x3>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
};
...

1
Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
View File

@ -58,6 +58,7 @@ properties:
- qcom,glymur-tsens
- qcom,hawi-tsens
- qcom,kaanapali-tsens
- qcom,maili-tsens
- qcom,milos-tsens
- qcom,nord-tsens
- qcom,msm8953-tsens

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -1690,6 +1690,8 @@ patternProperties:
description: Technologic Systems
"^techstar,.*":
description: Shenzhen Techstar Electronics Co., Ltd.
"^techvision,.*":
description: Techvision Intelligent Technology Co., Ltd
"^techwell,.*":
description: Techwell, Inc.
"^teejet,.*":

10
Documentation/driver-api/acpi/linuxized-acpica.rst
View File

@ -117,7 +117,7 @@ ACPICA Release
==============
The ACPICA project maintains its code base at the following repository URL:
https://github.com/acpica/acpica.git. As a rule, a release is made every
https://github.com/open-acpica/acpica.git. As a rule, a release is made every
month.
As the coding style adopted by the ACPICA project is not acceptable by
@ -173,7 +173,7 @@ illustrated in the following figure::
utility located in source/tools/acpisrc folder and a number of
scripts located in generate/linux folder.
B. acpica / master - "master" branch of the git repository at
<https://github.com/acpica/acpica.git>.
<https://github.com/open-acpica/acpica.git>.
C. linux-pm / linux-next - "linux-next" branch of the git repository at
<https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git>.
D. linux / master - "master" branch of the git repository at
@ -244,7 +244,7 @@ before they become available from the ACPICA release process.
Then the gen-patch.sh command can help to cherry-pick an ACPICA commit
from the ACPICA local repository::
$ git clone https://github.com/acpica/acpica
$ git clone https://github.com/open-acpica/acpica
$ cd acpica
$ generate/linux/gen-patch.sh -u [commit ID]
@ -259,7 +259,7 @@ before they become available from the ACPICA release process.
You can generate the ACPICA release series yourself and rebase your code on
top of the generated ACPICA release patches::
$ git clone https://github.com/acpica/acpica
$ git clone https://github.com/open-acpica/acpica
$ cd acpica
$ generate/linux/make-patches.sh -u [commit ID]
@ -273,7 +273,7 @@ before they become available from the ACPICA release process.
If you have local copies of both Linux and upstream ACPICA, you can generate
a diff file indicating the state of the current divergences::
# git clone https://github.com/acpica/acpica
# git clone https://github.com/open-acpica/acpica
# git clone https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
# cd acpica
# generate/linux/divergence.sh -s ../linux

58
Documentation/driver-api/clk.rst
View File

@ -42,21 +42,8 @@ clock interface.
Common data structures and api
==============================
Below is the common struct clk_core definition from
drivers/clk/clk.c, modified for brevity::
struct clk_core {
const char *name;
const struct clk_ops *ops;
struct clk_hw *hw;
struct module *owner;
struct clk_core *parent;
const char **parent_names;
struct clk_core **parents;
u8 num_parents;
u8 new_parent_index;
...
};
.. kernel-doc:: drivers/clk/clk.c
:identifiers: struct clk_core
The members above make up the core of the clk tree topology. The clk
api itself defines several driver-facing functions which operate on
@ -64,38 +51,17 @@ struct clk. That api is documented in include/linux/clk.h.
Platforms and devices utilizing the common struct clk_core use the struct
clk_ops pointer in struct clk_core to perform the hardware-specific parts of
the operations defined in clk-provider.h::
the operations defined in clk-provider.h, and can set one or more
framework-level flags documented below.
struct clk_ops {
int (*prepare)(struct clk_hw *hw);
void (*unprepare)(struct clk_hw *hw);
int (*is_prepared)(struct clk_hw *hw);
void (*unprepare_unused)(struct clk_hw *hw);
int (*enable)(struct clk_hw *hw);
void (*disable)(struct clk_hw *hw);
int (*is_enabled)(struct clk_hw *hw);
void (*disable_unused)(struct clk_hw *hw);
unsigned long (*recalc_rate)(struct clk_hw *hw,
unsigned long parent_rate);
int (*determine_rate)(struct clk_hw *hw,
struct clk_rate_request *req);
int (*set_parent)(struct clk_hw *hw, u8 index);
u8 (*get_parent)(struct clk_hw *hw);
int (*set_rate)(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate);
int (*set_rate_and_parent)(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate,
u8 index);
unsigned long (*recalc_accuracy)(struct clk_hw *hw,
unsigned long parent_accuracy);
int (*get_phase)(struct clk_hw *hw);
int (*set_phase)(struct clk_hw *hw, int degrees);
void (*init)(struct clk_hw *hw);
void (*debug_init)(struct clk_hw *hw,
struct dentry *dentry);
};
.. kernel-doc:: include/linux/clk-provider.h
:identifiers: struct clk_ops
Core flags
==========
.. kernel-doc:: include/linux/clk-provider.h
:doc: clk framework flags
Hardware clk implementations
============================

1
Documentation/driver-api/driver-model/devres.rst
View File

@ -248,6 +248,7 @@ CLOCK
devm_clk_put()
devm_clk_bulk_get()
devm_clk_bulk_get_all()
devm_clk_bulk_get_enable()
devm_clk_bulk_get_optional()
devm_get_clk_from_child()
devm_clk_hw_register()

4
Documentation/driver-api/pwrseq.rst
View File

@ -50,9 +50,9 @@ Consumer interface
The consumer API is aimed to be as simple as possible. The driver interested in
getting a descriptor from the power sequencer should call pwrseq_get() and
specify the name of the target it wants to reach in the sequence after calling
pwrseq_power_up(). The descriptor can be released by calling pwrseq_put() and
pwrseq_enable(). The descriptor can be released by calling pwrseq_put() and
the consumer can request the powering down of its target with
pwrseq_power_off(). Note that there is no guarantee that pwrseq_power_off()
pwrseq_disable(). Note that there is no guarantee that pwrseq_disable()
will have any effect as there may be multiple users of the underlying resources
who may keep them active.

6
Documentation/filesystems/ceph.rst
View File

@ -194,6 +194,12 @@ Mount Options
copies. Currently, it's only used in copy_file_range, which will revert
to the default VFS implementation if this option is used.
nearfull_sync
Force written data to stable storage when the cluster or file data pool is
marked NEARFULL. This restores the legacy client-side backpressure
behavior. By default, CephFS writes are not forced synchronous solely
because of NEARFULL.
recover_session=<no|clean>
Set auto reconnect mode in the case where the client is blocklisted. The
available modes are "no" and "clean". The default is "no".

43
Documentation/filesystems/f2fs.rst
View File

@ -415,7 +415,13 @@ lookup_mode=%s Control the directory lookup behavior for casefolded
auto F2FS determines the mode based on the
on-disk `SB_ENC_NO_COMPAT_FALLBACK_FL`
flag.
================== ========================================
resizable_tail_secno=%u Control the number of sections at the tail of the
filesystem reserved for online resizing. Pinned files
will only be allocated within sections 0 to
(MAIN_SECS - resizable_tail_secno) - 1. If set to 0
(default), there is no tail restriction unless running
on a zoned block device where conventional zones are
used.
======================== ============================================================
Debugfs Entries
@ -1043,6 +1049,41 @@ So, the key idea is, user can do any file operations on /dev/vdc, and
reclaim the space after the use, while the space is counted as /data.
That doesn't require modifying partition size and filesystem format.
Dynamic Device Aliasing Management
----------------------------------
In addition to static device aliasing by deleting the aliasing file, F2FS
supports dynamic management of device aliasing. This mechanism allows the system
to dynamically transition partition ownership between F2FS userdata and external
entities (e.g., zRAM, raw partition) based on system requirements without
deleting the master aliasing file or requiring unmount/remount.
The master aliasing file is created during the initial format of the file system
and remains as a persistent control entity (ioctl gateway) in the root directory.
- Partition Reservation (In-service to Aliased)
When a specific partition needs to be dedicated to external services (e.g., zRAM),
a user can reserve the device alias range via ioctl. The kernel resets GC victim
information for the target range, marks segments as in-use to prevent new
allocations, and triggers forced GC to migrate existing valid data out of the
range. Finally, it reserves these blocks in the SIT to effectively exclude the
device from the usable capacity.
- Partition Release (Aliased to In-service)
When external usage concludes, the space is reclaimed not by deleting the file,
but through the release ioctl. The kernel truncates blocks associated with
the file, releasing them back to general filesystem allocation.
.. code-block::
# f2fs_io dev_alias release /mnt/f2fs/vdc.file
# df -h
/dev/vdb 64G 753M 64G 2% /mnt/f2fs
# f2fs_io dev_alias reserve /mnt/f2fs/vdc.file
# df -h
/dev/vdb 64G 33G 32G 52% /mnt/f2fs
Per-file Read-Only Large Folio Support
--------------------------------------

4
Documentation/filesystems/fscrypt.rst
View File

@ -1237,6 +1237,10 @@ astute users may notice some differences in behavior:
- DAX (Direct Access) is not supported on encrypted files.
- Encrypted files cannot be used directly as swap files. To swap to
an encrypted file, set up a loopback device on top of it.
Alternatively, encrypted swap can use a dm-crypt device.
- The maximum length of an encrypted symlink is 2 bytes shorter than
the maximum length of an unencrypted symlink. For example, on an
EXT4 filesystem with a 4K block size, unencrypted symlinks can be up

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