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https://github.com/torvalds/linux.git
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Merge branch 'net-ethernet-mtk_eth_soc-improve-device-tree-handling'
Daniel Golle says:
====================
net: ethernet: mtk_eth_soc: improve device tree handling
This series further improves the mtk_eth_soc driver in preparation to
complete upstream support for the MediaTek MT7988 SoC family.
Frank Wunderlich's previous attempt to have the ethernet node included
in mt7988a.dtsi and cover support for MT7988 in the device tree bindings
was criticized for the way mtk_eth_soc references SRAM in device tree[1].
Having a 2nd 'reg' property, like introduced by commit ebb1e4f9cf
("net: ethernet: mtk_eth_soc: add support for in-SoC SRAM") isn't
acceptable and a dedicated "mmio-sram" node should be used instead.
In order to make the code more clean and readable, the existing
hardcoded offsets for the scratch ring, RX and TX rings are dropped in
favor of using the generic allocator. However, support for the hardcoded
offset of the SRAM itself being included as part of the Ethernet's "reg"
MMIO space is kept as it will still be required in order to support
existing legacy device trees of the MT7986 SoC family.
While at it also replace confusing error messages when using legacy
device trees without "interrupt-names" with a warning informing users
that they are using a legacy device tree.
[1]: https://patchwork.ozlabs.org/comment/3533543/
====================
Link: https://patch.msgid.link/cover.1751461762.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
commit
49402a628e
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@ -17,6 +17,7 @@ config NET_MEDIATEK_SOC
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select PINCTRL
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select PHYLINK
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select DIMLIB
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select GENERIC_ALLOCATOR
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select PAGE_POOL
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select PAGE_POOL_STATS
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select PCS_MTK_LYNXI
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@ -27,6 +27,7 @@
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#include <net/dsa.h>
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#include <net/dst_metadata.h>
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#include <net/page_pool/helpers.h>
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#include <linux/genalloc.h>
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#include "mtk_eth_soc.h"
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#include "mtk_wed.h"
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@ -1267,6 +1268,34 @@ static void *mtk_max_lro_buf_alloc(gfp_t gfp_mask)
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return (void *)data;
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}
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static void *mtk_dma_ring_alloc(struct mtk_eth *eth, size_t size,
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dma_addr_t *dma_handle, bool use_sram)
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{
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void *dma_ring;
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if (use_sram && eth->sram_pool) {
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dma_ring = (void *)gen_pool_alloc(eth->sram_pool, size);
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if (!dma_ring)
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return dma_ring;
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*dma_handle = gen_pool_virt_to_phys(eth->sram_pool,
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(unsigned long)dma_ring);
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} else {
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dma_ring = dma_alloc_coherent(eth->dma_dev, size, dma_handle,
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GFP_KERNEL);
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}
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return dma_ring;
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}
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static void mtk_dma_ring_free(struct mtk_eth *eth, size_t size, void *dma_ring,
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dma_addr_t dma_handle, bool in_sram)
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{
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if (in_sram && eth->sram_pool)
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gen_pool_free(eth->sram_pool, (unsigned long)dma_ring, size);
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else
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dma_free_coherent(eth->dma_dev, size, dma_ring, dma_handle);
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}
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/* the qdma core needs scratch memory to be setup */
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static int mtk_init_fq_dma(struct mtk_eth *eth)
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{
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@ -1276,13 +1305,8 @@ static int mtk_init_fq_dma(struct mtk_eth *eth)
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dma_addr_t dma_addr;
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int i, j, len;
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM))
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eth->scratch_ring = eth->sram_base;
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else
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eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
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cnt * soc->tx.desc_size,
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ð->phy_scratch_ring,
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GFP_KERNEL);
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eth->scratch_ring = mtk_dma_ring_alloc(eth, cnt * soc->tx.desc_size,
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ð->phy_scratch_ring, true);
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if (unlikely(!eth->scratch_ring))
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return -ENOMEM;
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@ -2620,14 +2644,7 @@ static int mtk_tx_alloc(struct mtk_eth *eth)
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if (!ring->buf)
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goto no_tx_mem;
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if (MTK_HAS_CAPS(soc->caps, MTK_SRAM)) {
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ring->dma = eth->sram_base + soc->tx.fq_dma_size * sz;
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ring->phys = eth->phy_scratch_ring + soc->tx.fq_dma_size * (dma_addr_t)sz;
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} else {
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ring->dma = dma_alloc_coherent(eth->dma_dev, ring_size * sz,
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&ring->phys, GFP_KERNEL);
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}
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ring->dma = mtk_dma_ring_alloc(eth, ring_size * sz, &ring->phys, true);
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if (!ring->dma)
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goto no_tx_mem;
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@ -2726,10 +2743,10 @@ static void mtk_tx_clean(struct mtk_eth *eth)
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kfree(ring->buf);
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ring->buf = NULL;
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}
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if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
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dma_free_coherent(eth->dma_dev,
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ring->dma_size * soc->tx.desc_size,
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ring->dma, ring->phys);
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if (ring->dma) {
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mtk_dma_ring_free(eth, ring->dma_size * soc->tx.desc_size,
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ring->dma, ring->phys, true);
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ring->dma = NULL;
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}
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@ -2746,14 +2763,9 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
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const struct mtk_reg_map *reg_map = eth->soc->reg_map;
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const struct mtk_soc_data *soc = eth->soc;
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struct mtk_rx_ring *ring;
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int rx_data_len, rx_dma_size, tx_ring_size;
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int rx_data_len, rx_dma_size;
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int i;
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
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tx_ring_size = MTK_QDMA_RING_SIZE;
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else
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tx_ring_size = soc->tx.dma_size;
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if (rx_flag == MTK_RX_FLAGS_QDMA) {
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if (ring_no)
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return -EINVAL;
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@ -2788,20 +2800,10 @@ static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
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ring->page_pool = pp;
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}
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if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
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rx_flag != MTK_RX_FLAGS_NORMAL) {
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ring->dma = dma_alloc_coherent(eth->dma_dev,
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rx_dma_size * eth->soc->rx.desc_size,
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&ring->phys, GFP_KERNEL);
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} else {
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struct mtk_tx_ring *tx_ring = ð->tx_ring;
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ring->dma = tx_ring->dma + tx_ring_size *
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eth->soc->tx.desc_size * (ring_no + 1);
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ring->phys = tx_ring->phys + tx_ring_size *
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eth->soc->tx.desc_size * (ring_no + 1);
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}
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ring->dma = mtk_dma_ring_alloc(eth,
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rx_dma_size * eth->soc->rx.desc_size,
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&ring->phys,
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rx_flag == MTK_RX_FLAGS_NORMAL);
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if (!ring->dma)
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return -ENOMEM;
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@ -2916,10 +2918,9 @@ static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_
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ring->data = NULL;
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}
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if (!in_sram && ring->dma) {
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dma_free_coherent(eth->dma_dev,
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ring->dma_size * eth->soc->rx.desc_size,
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ring->dma, ring->phys);
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if (ring->dma) {
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mtk_dma_ring_free(eth, ring->dma_size * eth->soc->rx.desc_size,
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ring->dma, ring->phys, in_sram);
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ring->dma = NULL;
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}
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@ -3287,15 +3288,16 @@ static void mtk_dma_free(struct mtk_eth *eth)
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netdev_tx_reset_subqueue(eth->netdev[i], j);
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}
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if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
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dma_free_coherent(eth->dma_dev,
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MTK_QDMA_RING_SIZE * soc->tx.desc_size,
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eth->scratch_ring, eth->phy_scratch_ring);
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if (eth->scratch_ring) {
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mtk_dma_ring_free(eth, soc->tx.fq_dma_size * soc->tx.desc_size,
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eth->scratch_ring, eth->phy_scratch_ring,
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true);
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eth->scratch_ring = NULL;
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eth->phy_scratch_ring = 0;
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}
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mtk_tx_clean(eth);
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mtk_rx_clean(eth, ð->rx_ring[0], MTK_HAS_CAPS(soc->caps, MTK_SRAM));
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mtk_rx_clean(eth, ð->rx_ring[0], true);
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mtk_rx_clean(eth, ð->rx_ring_qdma, false);
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if (eth->hwlro) {
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@ -3341,17 +3343,22 @@ static int mtk_get_irqs(struct platform_device *pdev, struct mtk_eth *eth)
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int i;
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/* future SoCs beginning with MT7988 should use named IRQs in dts */
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eth->irq[MTK_FE_IRQ_TX] = platform_get_irq_byname(pdev, "fe1");
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eth->irq[MTK_FE_IRQ_RX] = platform_get_irq_byname(pdev, "fe2");
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eth->irq[MTK_FE_IRQ_TX] = platform_get_irq_byname_optional(pdev, "fe1");
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eth->irq[MTK_FE_IRQ_RX] = platform_get_irq_byname_optional(pdev, "fe2");
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if (eth->irq[MTK_FE_IRQ_TX] >= 0 && eth->irq[MTK_FE_IRQ_RX] >= 0)
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return 0;
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/* only use legacy mode if platform_get_irq_byname returned -ENXIO */
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/* only use legacy mode if platform_get_irq_byname_optional returned -ENXIO */
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if (eth->irq[MTK_FE_IRQ_TX] != -ENXIO)
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return eth->irq[MTK_FE_IRQ_TX];
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return dev_err_probe(&pdev->dev, eth->irq[MTK_FE_IRQ_TX],
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"Error requesting FE TX IRQ\n");
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if (eth->irq[MTK_FE_IRQ_RX] != -ENXIO)
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return eth->irq[MTK_FE_IRQ_RX];
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return dev_err_probe(&pdev->dev, eth->irq[MTK_FE_IRQ_RX],
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"Error requesting FE RX IRQ\n");
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if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT))
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dev_warn(&pdev->dev, "legacy DT: missing interrupt-names.");
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/* legacy way:
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* On MTK_SHARED_INT SoCs (MT7621 + MT7628) the first IRQ is taken
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@ -5002,9 +5009,30 @@ static int mtk_sgmii_init(struct mtk_eth *eth)
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return 0;
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}
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static int mtk_setup_legacy_sram(struct mtk_eth *eth, struct resource *res)
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{
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dev_warn(eth->dev, "legacy DT: using hard-coded SRAM offset.\n");
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if (res->start + MTK_ETH_SRAM_OFFSET + MTK_ETH_NETSYS_V2_SRAM_SIZE - 1 >
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res->end)
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return -EINVAL;
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eth->sram_pool = devm_gen_pool_create(eth->dev,
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const_ilog2(MTK_ETH_SRAM_GRANULARITY),
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NUMA_NO_NODE, dev_name(eth->dev));
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if (IS_ERR(eth->sram_pool))
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return PTR_ERR(eth->sram_pool);
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return gen_pool_add_virt(eth->sram_pool,
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(unsigned long)eth->base + MTK_ETH_SRAM_OFFSET,
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res->start + MTK_ETH_SRAM_OFFSET,
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MTK_ETH_NETSYS_V2_SRAM_SIZE, NUMA_NO_NODE);
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}
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static int mtk_probe(struct platform_device *pdev)
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{
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struct resource *res = NULL, *res_sram;
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struct resource *res = NULL;
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struct device_node *mac_np;
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struct mtk_eth *eth;
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int err, i;
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@ -5024,20 +5052,6 @@ static int mtk_probe(struct platform_device *pdev)
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
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eth->ip_align = NET_IP_ALIGN;
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
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/* SRAM is actual memory and supports transparent access just like DRAM.
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* Hence we don't require __iomem being set and don't need to use accessor
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* functions to read from or write to SRAM.
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*/
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if (mtk_is_netsys_v3_or_greater(eth)) {
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eth->sram_base = (void __force *)devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(eth->sram_base))
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return PTR_ERR(eth->sram_base);
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} else {
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eth->sram_base = (void __force *)eth->base + MTK_ETH_SRAM_OFFSET;
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}
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
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err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
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if (!err)
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@ -5112,16 +5126,21 @@ static int mtk_probe(struct platform_device *pdev)
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err = -EINVAL;
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goto err_destroy_sgmii;
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}
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM)) {
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if (mtk_is_netsys_v3_or_greater(eth)) {
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res_sram = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res_sram) {
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eth->sram_pool = of_gen_pool_get(pdev->dev.of_node,
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"sram", 0);
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if (!eth->sram_pool) {
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if (!mtk_is_netsys_v3_or_greater(eth)) {
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err = mtk_setup_legacy_sram(eth, res);
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if (err)
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goto err_destroy_sgmii;
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} else {
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dev_err(&pdev->dev,
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"Could not get SRAM pool\n");
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err = -EINVAL;
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goto err_destroy_sgmii;
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}
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eth->phy_scratch_ring = res_sram->start;
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} else {
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eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
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}
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}
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}
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@ -141,8 +141,10 @@
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#define MTK_GDMA_MAC_ADRH(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \
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0x54C : 0x50C + (_x * 0x1000); })
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/* Internal SRAM offset */
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#define MTK_ETH_SRAM_OFFSET 0x40000
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/* legacy DT support for internal SRAM */
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#define MTK_ETH_SRAM_OFFSET 0x40000
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#define MTK_ETH_SRAM_GRANULARITY 32
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#define MTK_ETH_NETSYS_V2_SRAM_SIZE 0x40000
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/* FE global misc reg*/
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#define MTK_FE_GLO_MISC 0x124
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@ -1243,8 +1245,9 @@ struct mtk_soc_data {
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/* struct mtk_eth - This is the main datasructure for holding the state
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* of the driver
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* @dev: The device pointer
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* @dev: The device pointer used for dma mapping/alloc
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* @dma_dev: The device pointer used for dma mapping/alloc
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* @base: The mapped register i/o base
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* @sram_pool: Pointer to SRAM pool used for DMA descriptor rings
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* @page_lock: Make sure that register operations are atomic
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* @tx_irq__lock: Make sure that IRQ register operations are atomic
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* @rx_irq__lock: Make sure that IRQ register operations are atomic
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@ -1290,7 +1293,7 @@ struct mtk_eth {
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struct device *dev;
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struct device *dma_dev;
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void __iomem *base;
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void *sram_base;
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struct gen_pool *sram_pool;
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spinlock_t page_lock;
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spinlock_t tx_irq_lock;
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spinlock_t rx_irq_lock;
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