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drm/amd/display: Update DCN32 and DCN321 SR latencies
Update worst case SR latencies according to values measured by hardware team. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -121,8 +121,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_2_soc = {
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},
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},
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.num_states = 1,
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.sr_exit_time_us = 5.20,
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.sr_enter_plus_exit_time_us = 9.60,
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.sr_exit_time_us = 20.16,
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.sr_enter_plus_exit_time_us = 27.13,
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.sr_exit_z8_time_us = 285.0,
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.sr_enter_plus_exit_z8_time_us = 320,
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.writeback_latency_us = 12.0,
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@ -119,8 +119,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_21_soc = {
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},
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},
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.num_states = 1,
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.sr_exit_time_us = 5.20,
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.sr_enter_plus_exit_time_us = 9.60,
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.sr_exit_time_us = 12.36,
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.sr_enter_plus_exit_time_us = 16.72,
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.sr_exit_z8_time_us = 285.0,
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.sr_enter_plus_exit_z8_time_us = 320,
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.writeback_latency_us = 12.0,
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