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drm/amdgpu: force complete the MES ring fences on reset

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The MES scheduler ring has no drm scheduler (no_scheduler = true), so it is
skipped by the force-completion loop in amdgpu_device_pre_asic_reset(). It uses
a polling fence whose hw value lives in wb (GTT) memory and survives a MODE1
reset, while fence_drv.sync_seq keeps advancing for every packet.

When the reset is triggered because MES itself stopped responding, the
timed-out packets advance sync_seq past the last hw fence value MES wrote.
After resume the first MES submission polls forever on a seq that is never
written back, failing the resume and wedging the box on a second reset:

  amdgpu: MES ring buffer is full.
  amdgpu: *ERROR* ring gfx_0.0.0 test failed (-110)
  amdgpu: resume of IP block <gfx_v11_0> failed -110
  amdgpu: GPU reset end with ret = -110

Force complete the MES scheduler ring fences together with the scheduler rings
so their hw fence is realigned to sync_seq.

v2: cover all XCCs (one scheduler ring each), not just mes.ring[0].

Cc: stable@vger.kernel.org
Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse Zhang 2026-08-13 12:27:53 +08:00 committed by Alex Deucher
parent 59db985bc9
commit 48dc279c30
1 changed files with 13 additions and 0 deletions
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13
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
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@ -5043,6 +5043,19 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
amdgpu_fence_driver_force_completion(ring, fence);
}
/*
* MES scheduler rings have no drm scheduler, so they are missed by the
* loop above. Realign their polling fence too (one per XCC), otherwise the
* first post-reset submission polls forever on a stale seq. sched.ready is
* only set while the driver owns the ring.
*/
for (i = 0; i < AMDGPU_MAX_MES_INST_PIPES; i++) {
struct amdgpu_ring *mes_ring = &adev->mes.ring[i];
if (mes_ring->fence_drv.initialized && mes_ring->sched.ready)
amdgpu_fence_driver_force_completion(mes_ring, fence);
}
amdgpu_fence_driver_isr_toggle(adev, false);
r = amdgpu_reset_prepare_hwcontext(adev, reset_context);