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perf/x86/intel: Add PMU support for Clearwater Forest

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From the PMU's perspective, Clearwater Forest is similar to the previous
generation Sierra Forest.

The key differences are the ARCH PEBS feature and the new added 3 fixed
counters for topdown L1 metrics events.

The ARCH PEBS is supported in the following patches. This patch provides
support for basic perfmon features and 3 new added fixed counters.

Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lkml.kernel.org/r/20250415114428.341182-3-dapeng1.mi@linux.intel.com
This commit is contained in:
Dapeng Mi 2025-04-15 11:44:08 +00:00 committed by Ingo Molnar
parent b02b41c827
commit 48d66c89dc
1 changed files with 24 additions and 0 deletions
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24
arch/x86/events/intel/core.c
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@ -2224,6 +2224,18 @@ static struct extra_reg intel_cmt_extra_regs[] __read_mostly = {
EVENT_EXTRA_END
};
EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound_skt, "event=0x9c,umask=0x01");
EVENT_ATTR_STR(topdown-retiring, td_retiring_skt, "event=0xc2,umask=0x02");
EVENT_ATTR_STR(topdown-be-bound, td_be_bound_skt, "event=0xa4,umask=0x02");
static struct attribute *skt_events_attrs[] = {
EVENT_PTR(td_fe_bound_skt),
EVENT_PTR(td_retiring_skt),
EVENT_PTR(td_bad_spec_cmt),
EVENT_PTR(td_be_bound_skt),
NULL,
};
#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
#define KNL_MCDRAM_LOCAL BIT_ULL(21)
@ -7142,6 +7154,18 @@ __init int intel_pmu_init(void)
name = "crestmont";
break;
case INTEL_ATOM_DARKMONT_X:
intel_pmu_init_skt(NULL);
intel_pmu_pebs_data_source_cmt();
x86_pmu.pebs_latency_data = cmt_latency_data;
x86_pmu.get_event_constraints = cmt_get_event_constraints;
td_attr = skt_events_attrs;
mem_attr = grt_mem_attrs;
extra_attr = cmt_format_attr;
pr_cont("Darkmont events, ");
name = "darkmont";
break;
case INTEL_WESTMERE:
case INTEL_WESTMERE_EP:
case INTEL_WESTMERE_EX: