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PCI: rockchip: dw: Double check LTSSM

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We saw a link failure after linkup which should fail to probe the device
actually. That was misleading for PCIe stack to scan the device. Add a
double check for that. If that happened, just try to link until the
timeout happened.

[    2.373308] rk-pcie fe180000.pcie: PCIe Linking... LTSSM is 0x3
[    2.455521] rk-pcie fe180000.pcie: PCIe Link up, LTSSM is 0x2
[    2.455658] rk-pcie fe180000.pcie: PCI host bridge to bus 0003:30

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I0f9bcbb42d77a80aa1cb533952427b71096240d6
This commit is contained in:
Shawn Lin 2023-03-21 17:41:14 +08:00 committed by Tao Huang
parent d031ad7267
commit 48b91619b8
1 changed files with 7 additions and 4 deletions
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11
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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@ -815,10 +815,13 @@ static int rk_pcie_establish_link(struct dw_pcie *pci)
* more for Gen switch.
*/
msleep(50);
dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(rk_pcie);
return 0;
/* In case link drop after linkup, double check it */
if (dw_pcie_link_up(pci)) {
dev_info(pci->dev, "PCIe Link up, LTSSM is 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
rk_pcie_debug_dump(rk_pcie);
return 0;
}
}
dev_info_ratelimited(pci->dev, "PCIe Linking... LTSSM is 0x%x\n",