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KVM: SVM: Emulate reads and writes to shadow stack MSRs

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Emulate shadow stack MSR access by reading and writing to the
corresponding fields in the VMCB.

Signed-off-by: John Allen <john.allen@amd.com>
[sean: mark VMCB_CET dirty/clean as appropriate]
Link: https://lore.kernel.org/r/20250919223258.1604852-36-seanjc@google.com
Signed-off-by: Sean Christopherson <seanjc@google.com>
This commit is contained in:
John Allen 2025-09-19 15:32:42 -07:00 committed by Sean Christopherson
parent 42ae644853
commit 48b2ec0d54
2 changed files with 23 additions and 1 deletions
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21
arch/x86/kvm/svm/svm.c
View File

@ -2767,6 +2767,15 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
if (guest_cpuid_is_intel_compatible(vcpu))
msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
break;
case MSR_IA32_S_CET:
msr_info->data = svm->vmcb->save.s_cet;
break;
case MSR_IA32_INT_SSP_TAB:
msr_info->data = svm->vmcb->save.isst_addr;
break;
case MSR_KVM_INTERNAL_GUEST_SSP:
msr_info->data = svm->vmcb->save.ssp;
break;
case MSR_TSC_AUX:
msr_info->data = svm->tsc_aux;
break;
@ -2999,6 +3008,18 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
svm->sysenter_esp_hi = guest_cpuid_is_intel_compatible(vcpu) ? (data >> 32) : 0;
break;
case MSR_IA32_S_CET:
svm->vmcb->save.s_cet = data;
vmcb_mark_dirty(svm->vmcb01.ptr, VMCB_CET);
break;
case MSR_IA32_INT_SSP_TAB:
svm->vmcb->save.isst_addr = data;
vmcb_mark_dirty(svm->vmcb01.ptr, VMCB_CET);
break;
case MSR_KVM_INTERNAL_GUEST_SSP:
svm->vmcb->save.ssp = data;
vmcb_mark_dirty(svm->vmcb01.ptr, VMCB_CET);
break;
case MSR_TSC_AUX:
/*
* TSC_AUX is always virtualized for SEV-ES guests when the

3
arch/x86/kvm/svm/svm.h
View File

@ -74,6 +74,7 @@ enum {
* AVIC PHYSICAL_TABLE pointer,
* AVIC LOGICAL_TABLE pointer
*/
VMCB_CET, /* S_CET, SSP, ISST_ADDR */
VMCB_SW = 31, /* Reserved for hypervisor/software use */
};
@ -82,7 +83,7 @@ enum {
(1U << VMCB_ASID) | (1U << VMCB_INTR) | \
(1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \
(1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \
(1U << VMCB_LBR) | (1U << VMCB_AVIC) | \
(1U << VMCB_LBR) | (1U << VMCB_AVIC) | (1U << VMCB_CET) | \
(1U << VMCB_SW))
/* TPR and CR2 are always written before VMRUN */