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staging: iio: meter: ade7854: Fix alignment for DMA safety
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: Rodrigo Siqueira <rodrigosiqueiramelo@gmail.com> Link: https://lore.kernel.org/r/20220807151218.656881-4-jic23@kernel.org
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@ -162,7 +162,7 @@ struct ade7854_state {
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int bits);
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int irq;
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struct mutex buf_lock;
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u8 tx[ADE7854_MAX_TX] ____cacheline_aligned;
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u8 tx[ADE7854_MAX_TX] __aligned(IIO_DMA_MINALIGN);
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u8 rx[ADE7854_MAX_RX];
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};
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