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drm/amdgpu: move tlb invalidation to mes sched pipe
The heavy weight shootdown need special handling in MES sched pipe Signed-off-by: Shaoyun Liu <shaoyun.liu@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -566,7 +566,8 @@ static int mes_v12_1_misc_op(struct amdgpu_mes *mes,
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union MESAPI__MISC misc_pkt;
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int pipe;
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if (mes->adev->enable_uni_mes)
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/*OP_WRM_REG_WR_WAIT is used to do tlb invalidation which need to be handled in sched pipe for gfx_12_1.*/
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if (mes->adev->enable_uni_mes && input->op != MES_MISC_OP_WRM_REG_WR_WAIT)
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pipe = AMDGPU_MES_KIQ_PIPE;
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else
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pipe = AMDGPU_MES_SCHED_PIPE;
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@ -960,7 +961,7 @@ static int mes_v12_1_inv_tlbs_pasid(struct amdgpu_mes *mes,
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if (ret < 0)
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return -EINVAL;
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mes_inv_tlbs.invalidate_tlbs.hub_id = ret;
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return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_KIQ_PIPE,
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return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, AMDGPU_MES_SCHED_PIPE,
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&mes_inv_tlbs, sizeof(mes_inv_tlbs),
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offsetof(union MESAPI__INV_TLBS, api_status));
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