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drm fixes for 6.15-rc8/final

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edid:
 - fix HDR metadata reset
 
 amdgpu:
 - Hibernate fix
 
 xe:
 - Make sure to check all forcewakes when dumping mocs
 - Fix wrong use of read64 on 32b register
 - Synchronize Panther Lake PCI IDs
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Merge tag 'drm-fixes-2025-05-24' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
 "Weekly drm fixes pull, on target to be quiet, just one amdgpu, one
  edid and a few minor xe fixes.

  edid:
   - fix HDR metadata reset

  amdgpu:
   - Hibernate fix

  xe:
   - Make sure to check all forcewakes when dumping mocs
   - Fix wrong use of read64 on 32b register
   - Synchronize Panther Lake PCI IDs"

* tag 'drm-fixes-2025-05-24' of https://gitlab.freedesktop.org/drm/kernel:
  drm/xe/ptl: Update the PTL pci id table
  drm/xe: Use xe_mmio_read32() to read mtcfg register
  drm/xe/mocs: Check if all domains awake
  Revert "drm/amd: Keep display off while going into S4"
  drm/edid: fixed the bug that hdr metadata was not reset
This commit is contained in:
Linus Torvalds 2025-05-23 15:17:55 -07:00
commit 4856ebd997
5 changed files with 16 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
View File

@ -3469,11 +3469,6 @@ static int dm_resume(struct amdgpu_ip_block *ip_block)
return 0;
}
/* leave display off for S4 sequence */
if (adev->in_s4)
return 0;
/* Recreate dc_state - DC invalidates it when setting power state to S3. */
dc_state_release(dm_state->context);
dm_state->context = dc_state_create(dm->dc, NULL);

1
drivers/gpu/drm/drm_edid.c
View File

@ -6596,6 +6596,7 @@ static void drm_reset_display_info(struct drm_connector *connector)
info->has_hdmi_infoframe = false;
info->rgb_quant_range_selectable = false;
memset(&info->hdmi, 0, sizeof(info->hdmi));
memset(&connector->hdr_sink_metadata, 0, sizeof(connector->hdr_sink_metadata));
info->edid_hdmi_rgb444_dc_modes = 0;
info->edid_hdmi_ycbcr444_dc_modes = 0;

10
drivers/gpu/drm/xe/xe_mmio.c
View File

@ -75,12 +75,12 @@ static void mmio_multi_tile_setup(struct xe_device *xe, size_t tile_mmio_size)
* is fine as it's going to the root tile's mmio, that's
* guaranteed to be initialized earlier in xe_mmio_probe_early()
*/
mtcfg = xe_mmio_read64_2x32(mmio, XEHP_MTCFG_ADDR);
mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);
tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
if (tile_count < xe->info.tile_count) {
drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
xe->info.tile_count, tile_count);
xe->info.tile_count, tile_count);
xe->info.tile_count = tile_count;
/*
@ -128,7 +128,7 @@ int xe_mmio_probe_early(struct xe_device *xe)
*/
xe->mmio.size = pci_resource_len(pdev, GTTMMADR_BAR);
xe->mmio.regs = pci_iomap(pdev, GTTMMADR_BAR, 0);
if (xe->mmio.regs == NULL) {
if (!xe->mmio.regs) {
drm_err(&xe->drm, "failed to map registers\n");
return -EIO;
}
@ -309,8 +309,8 @@ u64 xe_mmio_read64_2x32(struct xe_mmio *mmio, struct xe_reg reg)
return (u64)udw << 32 | ldw;
}
static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val, u32 timeout_us,
u32 *out_val, bool atomic, bool expect_match)
static int __xe_mmio_wait32(struct xe_mmio *mmio, struct xe_reg reg, u32 mask, u32 val,
u32 timeout_us, u32 *out_val, bool atomic, bool expect_match)
{
ktime_t cur = ktime_get_raw();
const ktime_t end = ktime_add_us(cur, timeout_us);

11
drivers/gpu/drm/xe/xe_mocs.c
View File

@ -775,22 +775,23 @@ void xe_mocs_init(struct xe_gt *gt)
void xe_mocs_dump(struct xe_gt *gt, struct drm_printer *p)
{
struct xe_device *xe = gt_to_xe(gt);
enum xe_force_wake_domains domain;
struct xe_mocs_info table;
unsigned int fw_ref, flags;
flags = get_mocs_settings(xe, &table);
domain = flags & HAS_LNCF_MOCS ? XE_FORCEWAKE_ALL : XE_FW_GT;
xe_pm_runtime_get_noresume(xe);
fw_ref = xe_force_wake_get(gt_to_fw(gt),
flags & HAS_LNCF_MOCS ?
XE_FORCEWAKE_ALL : XE_FW_GT);
if (!fw_ref)
fw_ref = xe_force_wake_get(gt_to_fw(gt), domain);
if (!xe_force_wake_ref_has_domain(fw_ref, domain))
goto err_fw;
table.ops->dump(&table, flags, gt, p);
xe_force_wake_put(gt_to_fw(gt), fw_ref);
err_fw:
xe_force_wake_put(gt_to_fw(gt), fw_ref);
xe_pm_runtime_put(xe);
}

4
include/drm/intel/pciids.h
View File

@ -861,6 +861,10 @@
MACRO__(0xB081, ## __VA_ARGS__), \
MACRO__(0xB082, ## __VA_ARGS__), \
MACRO__(0xB083, ## __VA_ARGS__), \
MACRO__(0xB084, ## __VA_ARGS__), \
MACRO__(0xB085, ## __VA_ARGS__), \
MACRO__(0xB086, ## __VA_ARGS__), \
MACRO__(0xB087, ## __VA_ARGS__), \
MACRO__(0xB08F, ## __VA_ARGS__), \
MACRO__(0xB090, ## __VA_ARGS__), \
MACRO__(0xB0A0, ## __VA_ARGS__), \