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Merge branch 'net-stmmac-start-to-shrink-memory-usage'

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Russell King says:

====================
net: stmmac: start to shrink memory usage

Start shrinking stmmac's memory usage by avoiding using "int" for
members that are only used for 0/1 (boolean) values, or values that
can't be larger than 255.

In addition, as struct stmmac_dma_cfg is approximately a cache line,
shrinks below a cache line as a result of this patch set, and is
required, there is no point separately allocating this from
struct plat_stmmacenet_data. Embed it into the end of this struct
and set the existing pointer to avoid large wide-spread changes.

Lastly, add documentation for struct stmmac_dma_cfg, and document
the stmmac clocks as best we can given the driver history.
====================

Link: https://patch.msgid.link/aa6VEsmBK-S9eNYU@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2026-03-10 19:54:43 -07:00
commit 482aac8b56
23 changed files with 240 additions and 201 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/net/ethernet/stmicro/stmmac/common.h
View File

@ -446,8 +446,8 @@ struct dma_features {
unsigned int number_rx_channel;
unsigned int number_tx_channel;
/* TX and RX number of queues */
unsigned int number_rx_queues;
unsigned int number_tx_queues;
u8 number_rx_queues;
u8 number_tx_queues;
/* PPS output */
unsigned int pps_out_num;
/* Number of Traffic Classes */

2
drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c
View File

@ -88,7 +88,7 @@ static int dwc_eth_dwmac_config_dt(struct platform_device *pdev,
plat_dat->core_type = DWMAC_CORE_GMAC4;
plat_dat->dma_cfg->aal = 1;
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
plat_dat->pmt = 1;
plat_dat->pmt = true;
return 0;
}

2
drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
View File

@ -42,8 +42,8 @@
struct imx_priv_data;
struct imx_dwmac_ops {
u32 addr_width;
u32 flags;
u8 addr_width;
bool mac_rgmii_txclk_auto_adj;
int (*fix_soc_reset)(struct stmmac_priv *priv);

7
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
View File

@ -566,7 +566,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->clk_csr = STMMAC_CSR_20_35M;
plat->core_type = DWMAC_CORE_GMAC;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
plat->mdio_bus_data->needs_reset = true;
}
@ -1251,11 +1251,6 @@ static int intel_eth_pci_probe(struct pci_dev *pdev,
if (!plat->mdio_bus_data)
return -ENOMEM;
plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
GFP_KERNEL);
if (!plat->dma_cfg)
return -ENOMEM;
plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
sizeof(*plat->safety_feat_cfg),
GFP_KERNEL);

6
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
View File

@ -94,7 +94,7 @@ static void loongson_default_data(struct pci_dev *pdev,
/* clk_csr_i = 100-150MHz & MDC = clk_csr_i/62 */
plat->clk_csr = STMMAC_CSR_100_150M;
plat->core_type = DWMAC_CORE_GMAC;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
/* Increase the default value for multicast hash bins */
plat->multicast_filter_bins = 256;
@ -513,10 +513,6 @@ static int loongson_dwmac_probe(struct pci_dev *pdev, const struct pci_device_id
if (!plat->mdio_bus_data)
return -ENOMEM;
plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
if (!plat->dma_cfg)
return -ENOMEM;
ld = devm_kzalloc(&pdev->dev, sizeof(*ld), GFP_KERNEL);
if (!ld)
return -ENOMEM;

8
drivers/net/ethernet/stmicro/stmmac/dwmac-mediatek.c
View File

@ -93,9 +93,9 @@ struct mediatek_dwmac_variant {
const char * const *clk_list;
int num_clks;
u32 dma_bit_mask;
u32 rx_delay_max;
u32 tx_delay_max;
u8 dma_bit_mask;
};
/* list of clocks required for mac */
@ -268,9 +268,9 @@ static const struct mediatek_dwmac_variant mt2712_gmac_variant = {
.dwmac_set_delay = mt2712_set_delay,
.clk_list = mt2712_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt2712_dwmac_clk_l),
.dma_bit_mask = 33,
.rx_delay_max = 17600,
.tx_delay_max = 17600,
.dma_bit_mask = 33,
};
static int mt8195_set_interface(struct mediatek_dwmac_plat_data *plat,
@ -418,9 +418,9 @@ static const struct mediatek_dwmac_variant mt8195_gmac_variant = {
.dwmac_set_delay = mt8195_set_delay,
.clk_list = mt8195_dwmac_clk_l,
.num_clks = ARRAY_SIZE(mt8195_dwmac_clk_l),
.dma_bit_mask = 35,
.rx_delay_max = 9280,
.tx_delay_max = 9280,
.dma_bit_mask = 35,
};
static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
@ -564,7 +564,7 @@ static int mediatek_dwmac_common_data(struct platform_device *pdev,
plat->flags &= ~STMMAC_FLAG_USE_PHY_WOL;
else
plat->flags |= STMMAC_FLAG_USE_PHY_WOL;
plat->riwt_off = 1;
plat->riwt_off = true;
plat->maxmtu = ETH_DATA_LEN;
plat->host_dma_width = priv_plat->variant->dma_bit_mask;
plat->bsp_priv = priv_plat;

4
drivers/net/ethernet/stmicro/stmmac/dwmac-motorcomm.c
View File

@ -218,10 +218,6 @@ motorcomm_default_plat_data(struct pci_dev *pdev)
if (!plat->mdio_bus_data)
return NULL;
plat->dma_cfg = devm_kzalloc(dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
if (!plat->dma_cfg)
return NULL;
plat->axi = devm_kzalloc(dev, sizeof(*plat->axi), GFP_KERNEL);
if (!plat->axi)
return NULL;

4
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
View File

@ -91,8 +91,8 @@ struct ethqos_emac_driver_data {
unsigned int num_rgmii_por;
bool rgmii_config_loopback_en;
bool has_emac_ge_3;
u8 dma_addr_width;
const char *link_clk_name;
u32 dma_addr_width;
struct dwmac4_addrs dwmac4_addrs;
bool needs_sgmii_loopback;
};
@ -817,7 +817,7 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
plat_dat->core_type = DWMAC_CORE_GMAC4;
if (ethqos->has_emac_ge_3)
plat_dat->dwmac4_addrs = &data->dwmac4_addrs;
plat_dat->pmt = 1;
plat_dat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat_dat->flags |= STMMAC_FLAG_TSO_EN;
if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))

2
drivers/net/ethernet/stmicro/stmmac/dwmac-s32.c
View File

@ -163,7 +163,7 @@ static int s32_dwmac_probe(struct platform_device *pdev)
/* S32CC core feature set */
plat->core_type = DWMAC_CORE_GMAC4;
plat->pmt = 1;
plat->pmt = true;
plat->flags |= STMMAC_FLAG_SPH_DISABLE;
plat->rx_fifo_size = 20480;
plat->tx_fifo_size = 20480;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
View File

@ -565,7 +565,7 @@ static void socfpga_gen5_setup_plat_dat(struct socfpga_dwmac *dwmac)
plat_dat->core_type = DWMAC_CORE_GMAC;
/* Rx watchdog timer in dwmac is buggy in this hw */
plat_dat->riwt_off = 1;
plat_dat->riwt_off = true;
}
static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac)

4
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
View File

@ -718,7 +718,7 @@ static void sun8i_dwmac_set_filter(struct mac_device_info *hw,
static void sun8i_dwmac_flow_ctrl(struct mac_device_info *hw,
unsigned int duplex, unsigned int fc,
unsigned int pause_time, u32 tx_cnt)
unsigned int pause_time, u8 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
u32 v;
@ -1179,7 +1179,7 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
* hardware features were copied from Allwinner drivers.
*/
plat_dat->rx_coe = STMMAC_RX_COE_TYPE2;
plat_dat->tx_coe = 1;
plat_dat->tx_coe = true;
plat_dat->flags |= STMMAC_FLAG_HAS_SUN8I;
plat_dat->bsp_priv = gmac;
plat_dat->init = sun8i_dwmac_init;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c
View File

@ -135,7 +135,7 @@ static int sun7i_gmac_probe(struct platform_device *pdev)
/* platform data specifying hardware features and callbacks.
* hardware features were copied from Allwinner drivers. */
plat_dat->tx_coe = 1;
plat_dat->tx_coe = true;
plat_dat->core_type = DWMAC_CORE_GMAC;
plat_dat->bsp_priv = gmac;
plat_dat->init = sun7i_gmac_init;

2
drivers/net/ethernet/stmicro/stmmac/dwmac-tegra.c
View File

@ -310,7 +310,7 @@ static int tegra_mgbe_probe(struct platform_device *pdev)
plat->core_type = DWMAC_CORE_XGMAC;
plat->flags |= STMMAC_FLAG_TSO_EN;
plat->pmt = 1;
plat->pmt = true;
plat->bsp_priv = mgbe;
if (!plat->mdio_node)

2
drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c
View File

@ -222,7 +222,7 @@ static void dwmac1000_set_filter(struct mac_device_info *hw,
static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time,
u32 tx_cnt)
u8 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
/* Set flow such that DZPQ in Mac Register 6 is 0,

2
drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c
View File

@ -126,7 +126,7 @@ static void dwmac100_set_filter(struct mac_device_info *hw,
static void dwmac100_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time,
u32 tx_cnt)
u8 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
unsigned int flow = MAC_FLOW_CTRL_ENABLE;

4
drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
View File

@ -547,11 +547,11 @@ static void dwmac4_set_filter(struct mac_device_info *hw,
static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time,
u32 tx_cnt)
u8 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
unsigned int flow = 0;
u32 queue = 0;
u8 queue;
pr_debug("GMAC Flow-Control:\n");
if (fc & FLOW_RX) {

4
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
View File

@ -355,10 +355,10 @@ static int dwxgmac2_host_mtl_irq_status(struct stmmac_priv *priv,
static void dwxgmac2_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time,
u32 tx_cnt)
u8 tx_cnt)
{
void __iomem *ioaddr = hw->pcsr;
u32 i;
u8 i;
if (fc & FLOW_RX)
writel(XGMAC_RFE, ioaddr + XGMAC_RX_FLOW_CTRL);

2
drivers/net/ethernet/stmicro/stmmac/hwif.h
View File

@ -352,7 +352,7 @@ struct stmmac_ops {
void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
/* Flow control setting */
void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
unsigned int fc, unsigned int pause_time, u32 tx_cnt);
unsigned int fc, unsigned int pause_time, u8 tx_cnt);
/* Set power management mode (e.g. magic frame) */
void (*pmt)(struct mac_device_info *hw, unsigned long mode);
/* Set/Get Unicast MAC addresses */

2
drivers/net/ethernet/stmicro/stmmac/stmmac.h
View File

@ -407,7 +407,7 @@ void stmmac_dvr_remove(struct device *dev);
int stmmac_dvr_probe(struct device *device,
struct plat_stmmacenet_data *plat_dat,
struct stmmac_resources *res);
int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
int stmmac_reinit_queues(struct net_device *dev, u8 rx_cnt, u8 tx_cnt);
int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
int stmmac_set_clk_tx_rate(void *bsp_priv, struct clk *clk_tx_i,
phy_interface_t interface, int speed);

227
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
View File

@ -264,10 +264,10 @@ static void stmmac_verify_args(void)
static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
{
u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
u32 queue;
u8 rx_queues_cnt = priv->plat->rx_queues_to_use;
u8 tx_queues_cnt = priv->plat->tx_queues_to_use;
u8 maxq = max(rx_queues_cnt, tx_queues_cnt);
u8 queue;
for (queue = 0; queue < maxq; queue++) {
struct stmmac_channel *ch = &priv->channel[queue];
@ -291,9 +291,9 @@ static void __stmmac_disable_all_queues(struct stmmac_priv *priv)
*/
static void stmmac_disable_all_queues(struct stmmac_priv *priv)
{
u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
u8 rx_queues_cnt = priv->plat->rx_queues_to_use;
struct stmmac_rx_queue *rx_q;
u32 queue;
u8 queue;
/* synchronize_rcu() needed for pending XDP buffers to drain */
for (queue = 0; queue < rx_queues_cnt; queue++) {
@ -313,10 +313,10 @@ static void stmmac_disable_all_queues(struct stmmac_priv *priv)
*/
static void stmmac_enable_all_queues(struct stmmac_priv *priv)
{
u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
u32 queue;
u8 rx_queues_cnt = priv->plat->rx_queues_to_use;
u8 tx_queues_cnt = priv->plat->tx_queues_to_use;
u8 maxq = max(rx_queues_cnt, tx_queues_cnt);
u8 queue;
for (queue = 0; queue < maxq; queue++) {
struct stmmac_channel *ch = &priv->channel[queue];
@ -377,8 +377,8 @@ static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
static bool stmmac_eee_tx_busy(struct stmmac_priv *priv)
{
u32 tx_cnt = priv->plat->tx_queues_to_use;
u32 queue;
u8 tx_cnt = priv->plat->tx_queues_to_use;
u8 queue;
/* check if all TX queues have the work finished */
for (queue = 0; queue < tx_cnt; queue++) {
@ -909,7 +909,7 @@ static int stmmac_legacy_serdes_power_up(struct stmmac_priv *priv)
static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex,
unsigned int flow_ctrl)
{
u32 tx_cnt = priv->plat->tx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
stmmac_flow_ctrl(priv, priv->hw, duplex, flow_ctrl, priv->pause_time,
tx_cnt);
@ -1410,10 +1410,10 @@ static int stmmac_phylink_setup(struct stmmac_priv *priv)
static void stmmac_display_rx_rings(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 rx_cnt = priv->plat->rx_queues_to_use;
u8 rx_cnt = priv->plat->rx_queues_to_use;
unsigned int desc_size;
void *head_rx;
u32 queue;
u8 queue;
/* Display RX rings */
for (queue = 0; queue < rx_cnt; queue++) {
@ -1438,10 +1438,10 @@ static void stmmac_display_rx_rings(struct stmmac_priv *priv,
static void stmmac_display_tx_rings(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 tx_cnt = priv->plat->tx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
unsigned int desc_size;
void *head_tx;
u32 queue;
u8 queue;
/* Display TX rings */
for (queue = 0; queue < tx_cnt; queue++) {
@ -1571,9 +1571,9 @@ static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv,
static void stmmac_clear_descriptors(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
u32 queue;
u8 rx_queue_cnt = priv->plat->rx_queues_to_use;
u8 tx_queue_cnt = priv->plat->tx_queues_to_use;
u8 queue;
/* Clear the RX descriptors */
for (queue = 0; queue < rx_queue_cnt; queue++)
@ -1891,7 +1891,7 @@ static int init_dma_rx_desc_rings(struct net_device *dev,
gfp_t flags)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 rx_count = priv->plat->rx_queues_to_use;
u8 rx_count = priv->plat->rx_queues_to_use;
int queue;
int ret;
@ -1985,8 +1985,8 @@ static int init_dma_tx_desc_rings(struct net_device *dev,
struct stmmac_dma_conf *dma_conf)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 tx_queue_cnt;
u32 queue;
u8 tx_queue_cnt;
u8 queue;
tx_queue_cnt = priv->plat->tx_queues_to_use;
@ -2057,8 +2057,8 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv,
*/
static void stmmac_free_tx_skbufs(struct stmmac_priv *priv)
{
u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
u32 queue;
u8 tx_queue_cnt = priv->plat->tx_queues_to_use;
u8 queue;
for (queue = 0; queue < tx_queue_cnt; queue++)
dma_free_tx_skbufs(priv, &priv->dma_conf, queue);
@ -2106,8 +2106,8 @@ static void __free_dma_rx_desc_resources(struct stmmac_priv *priv,
static void free_dma_rx_desc_resources(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 rx_count = priv->plat->rx_queues_to_use;
u32 queue;
u8 rx_count = priv->plat->rx_queues_to_use;
u8 queue;
/* Free RX queue resources */
for (queue = 0; queue < rx_count; queue++)
@ -2153,8 +2153,8 @@ static void __free_dma_tx_desc_resources(struct stmmac_priv *priv,
static void free_dma_tx_desc_resources(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 tx_count = priv->plat->tx_queues_to_use;
u32 queue;
u8 tx_count = priv->plat->tx_queues_to_use;
u8 queue;
/* Free TX queue resources */
for (queue = 0; queue < tx_count; queue++)
@ -2255,8 +2255,8 @@ static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 rx_count = priv->plat->rx_queues_to_use;
u32 queue;
u8 rx_count = priv->plat->rx_queues_to_use;
u8 queue;
int ret;
/* RX queues buffers and DMA */
@ -2331,8 +2331,8 @@ static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv,
struct stmmac_dma_conf *dma_conf)
{
u32 tx_count = priv->plat->tx_queues_to_use;
u32 queue;
u8 tx_count = priv->plat->tx_queues_to_use;
u8 queue;
int ret;
/* TX queues buffers and DMA */
@ -2396,8 +2396,8 @@ static void free_dma_desc_resources(struct stmmac_priv *priv,
*/
static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
{
u32 rx_queues_count = priv->plat->rx_queues_to_use;
int queue;
u8 rx_queues_count = priv->plat->rx_queues_to_use;
u8 queue;
u8 mode;
for (queue = 0; queue < rx_queues_count; queue++) {
@ -2460,10 +2460,10 @@ static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
{
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
u32 chan;
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
u8 dma_csr_ch = max(rx_channels_count, tx_channels_count);
u8 chan;
for (chan = 0; chan < dma_csr_ch; chan++) {
struct stmmac_channel *ch = &priv->channel[chan];
@ -2483,9 +2483,9 @@ static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv)
*/
static void stmmac_start_all_dma(struct stmmac_priv *priv)
{
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u32 chan = 0;
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
u8 chan;
for (chan = 0; chan < rx_channels_count; chan++)
stmmac_start_rx_dma(priv, chan);
@ -2502,9 +2502,9 @@ static void stmmac_start_all_dma(struct stmmac_priv *priv)
*/
static void stmmac_stop_all_dma(struct stmmac_priv *priv)
{
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u32 chan = 0;
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
u8 chan;
for (chan = 0; chan < rx_channels_count; chan++)
stmmac_stop_rx_dma(priv, chan);
@ -2521,14 +2521,14 @@ static void stmmac_stop_all_dma(struct stmmac_priv *priv)
*/
static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
{
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
int rxfifosz = priv->plat->rx_fifo_size;
int txfifosz = priv->plat->tx_fifo_size;
u32 txmode = 0;
u32 rxmode = 0;
u32 chan = 0;
u8 qmode = 0;
u8 chan;
if (rxfifosz == 0)
rxfifosz = priv->dma_cap.rx_fifo_size;
@ -3012,8 +3012,8 @@ static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
{
u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
int rxfifosz = priv->plat->rx_fifo_size;
int txfifosz = priv->plat->tx_fifo_size;
@ -3088,12 +3088,12 @@ static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir)
*/
static void stmmac_dma_interrupt(struct stmmac_priv *priv)
{
u32 tx_channel_count = priv->plat->tx_queues_to_use;
u32 rx_channel_count = priv->plat->rx_queues_to_use;
u32 channels_to_check = tx_channel_count > rx_channel_count ?
tx_channel_count : rx_channel_count;
u32 chan;
u8 tx_channel_count = priv->plat->tx_queues_to_use;
u8 rx_channel_count = priv->plat->rx_queues_to_use;
u8 channels_to_check = tx_channel_count > rx_channel_count ?
tx_channel_count : rx_channel_count;
int status[MAX_T(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
u8 chan;
/* Make sure we never check beyond our status buffer. */
if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
@ -3237,13 +3237,13 @@ static int stmmac_prereset_configure(struct stmmac_priv *priv)
*/
static int stmmac_init_dma_engine(struct stmmac_priv *priv)
{
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
u8 dma_csr_ch = max(rx_channels_count, tx_channels_count);
struct stmmac_rx_queue *rx_q;
struct stmmac_tx_queue *tx_q;
u32 chan = 0;
int ret = 0;
u8 chan;
ret = stmmac_prereset_configure(priv);
if (ret)
@ -3359,9 +3359,9 @@ static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t)
*/
static void stmmac_init_coalesce(struct stmmac_priv *priv)
{
u32 tx_channel_count = priv->plat->tx_queues_to_use;
u32 rx_channel_count = priv->plat->rx_queues_to_use;
u32 chan;
u8 tx_channel_count = priv->plat->tx_queues_to_use;
u8 rx_channel_count = priv->plat->rx_queues_to_use;
u8 chan;
for (chan = 0; chan < tx_channel_count; chan++) {
struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan];
@ -3378,9 +3378,9 @@ static void stmmac_init_coalesce(struct stmmac_priv *priv)
static void stmmac_set_rings_length(struct stmmac_priv *priv)
{
u32 rx_channels_count = priv->plat->rx_queues_to_use;
u32 tx_channels_count = priv->plat->tx_queues_to_use;
u32 chan;
u8 rx_channels_count = priv->plat->rx_queues_to_use;
u8 tx_channels_count = priv->plat->tx_queues_to_use;
u8 chan;
/* set TX ring length */
for (chan = 0; chan < tx_channels_count; chan++)
@ -3400,9 +3400,9 @@ static void stmmac_set_rings_length(struct stmmac_priv *priv)
*/
static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
{
u32 tx_queues_count = priv->plat->tx_queues_to_use;
u8 tx_queues_count = priv->plat->tx_queues_to_use;
u32 weight;
u32 queue;
u8 queue;
for (queue = 0; queue < tx_queues_count; queue++) {
weight = priv->plat->tx_queues_cfg[queue].weight;
@ -3417,9 +3417,9 @@ static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
*/
static void stmmac_configure_cbs(struct stmmac_priv *priv)
{
u32 tx_queues_count = priv->plat->tx_queues_to_use;
u8 tx_queues_count = priv->plat->tx_queues_to_use;
u32 mode_to_use;
u32 queue;
u8 queue;
/* queue 0 is reserved for legacy traffic */
for (queue = 1; queue < tx_queues_count; queue++) {
@ -3443,8 +3443,8 @@ static void stmmac_configure_cbs(struct stmmac_priv *priv)
*/
static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
{
u32 rx_queues_count = priv->plat->rx_queues_to_use;
u32 queue;
u8 rx_queues_count = priv->plat->rx_queues_to_use;
u8 queue;
u32 chan;
for (queue = 0; queue < rx_queues_count; queue++) {
@ -3460,8 +3460,8 @@ static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
*/
static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
{
u32 rx_queues_count = priv->plat->rx_queues_to_use;
u32 queue;
u8 rx_queues_count = priv->plat->rx_queues_to_use;
u8 queue;
u32 prio;
for (queue = 0; queue < rx_queues_count; queue++) {
@ -3480,8 +3480,8 @@ static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
*/
static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
{
u32 tx_queues_count = priv->plat->tx_queues_to_use;
u32 queue;
u8 tx_queues_count = priv->plat->tx_queues_to_use;
u8 queue;
u32 prio;
for (queue = 0; queue < tx_queues_count; queue++) {
@ -3500,9 +3500,9 @@ static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
*/
static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
{
u32 rx_queues_count = priv->plat->rx_queues_to_use;
u32 queue;
u8 rx_queues_count = priv->plat->rx_queues_to_use;
u8 packet;
u8 queue;
for (queue = 0; queue < rx_queues_count; queue++) {
/* no specific packet type routing specified for the queue */
@ -3537,8 +3537,8 @@ static void stmmac_mac_config_rss(struct stmmac_priv *priv)
*/
static void stmmac_mtl_configuration(struct stmmac_priv *priv)
{
u32 rx_queues_count = priv->plat->rx_queues_to_use;
u32 tx_queues_count = priv->plat->tx_queues_to_use;
u8 rx_queues_count = priv->plat->rx_queues_to_use;
u8 tx_queues_count = priv->plat->tx_queues_to_use;
if (tx_queues_count > 1)
stmmac_set_tx_queue_weight(priv);
@ -3606,10 +3606,10 @@ static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
static int stmmac_hw_setup(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 rx_cnt = priv->plat->rx_queues_to_use;
u32 tx_cnt = priv->plat->tx_queues_to_use;
u8 rx_cnt = priv->plat->rx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
bool sph_en;
u32 chan;
u8 chan;
int ret;
/* Make sure RX clock is enabled */
@ -4001,7 +4001,8 @@ static struct stmmac_dma_conf *
stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu)
{
struct stmmac_dma_conf *dma_conf;
int chan, bfsize, ret;
int bfsize, ret;
u8 chan;
dma_conf = kzalloc_obj(*dma_conf);
if (!dma_conf) {
@ -4076,7 +4077,7 @@ static int __stmmac_open(struct net_device *dev,
struct stmmac_dma_conf *dma_conf)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 chan;
u8 chan;
int ret;
for (int i = 0; i < MTL_MAX_TX_QUEUES; i++)
@ -4175,7 +4176,7 @@ static int stmmac_open(struct net_device *dev)
static void __stmmac_release(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 chan;
u8 chan;
/* Stop and disconnect the PHY */
phylink_stop(priv->phylink);
@ -6123,7 +6124,7 @@ static int stmmac_set_features(struct net_device *netdev,
if (priv->sph_capable) {
bool sph_en = (priv->hw->rx_csum > 0) && priv->sph_active;
u32 chan;
u8 chan;
for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
@ -6143,11 +6144,11 @@ static int stmmac_set_features(struct net_device *netdev,
static void stmmac_common_interrupt(struct stmmac_priv *priv)
{
u32 rx_cnt = priv->plat->rx_queues_to_use;
u32 tx_cnt = priv->plat->tx_queues_to_use;
u32 queues_count;
u32 queue;
u8 rx_cnt = priv->plat->rx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
u8 queues_count;
bool xmac;
u8 queue;
xmac = dwmac_is_xmac(priv->plat->core_type);
queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
@ -6445,9 +6446,9 @@ static int stmmac_rings_status_show(struct seq_file *seq, void *v)
{
struct net_device *dev = seq->private;
struct stmmac_priv *priv = netdev_priv(dev);
u32 rx_count = priv->plat->rx_queues_to_use;
u32 tx_count = priv->plat->tx_queues_to_use;
u32 queue;
u8 rx_count = priv->plat->rx_queues_to_use;
u8 tx_count = priv->plat->tx_queues_to_use;
u8 queue;
if ((dev->flags & IFF_UP) == 0)
return 0;
@ -6572,9 +6573,9 @@ static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
priv->dma_cap.number_rx_channel);
seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
priv->dma_cap.number_tx_channel);
seq_printf(seq, "\tNumber of Additional RX queues: %d\n",
seq_printf(seq, "\tNumber of Additional RX queues: %u\n",
priv->dma_cap.number_rx_queues);
seq_printf(seq, "\tNumber of Additional TX queues: %d\n",
seq_printf(seq, "\tNumber of Additional TX queues: %u\n",
priv->dma_cap.number_tx_queues);
seq_printf(seq, "\tEnhanced descriptors: %s\n",
(priv->dma_cap.enh_desc) ? "Y" : "N");
@ -7043,7 +7044,7 @@ void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue)
void stmmac_xdp_release(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 chan;
u8 chan;
/* Ensure tx function is not running */
netif_tx_disable(dev);
@ -7076,14 +7077,14 @@ void stmmac_xdp_release(struct net_device *dev)
int stmmac_xdp_open(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 rx_cnt = priv->plat->rx_queues_to_use;
u32 tx_cnt = priv->plat->tx_queues_to_use;
u32 dma_csr_ch = max(rx_cnt, tx_cnt);
u8 rx_cnt = priv->plat->rx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
u8 dma_csr_ch = max(rx_cnt, tx_cnt);
struct stmmac_rx_queue *rx_q;
struct stmmac_tx_queue *tx_q;
u32 buf_size;
bool sph_en;
u32 chan;
u8 chan;
int ret;
ret = alloc_dma_desc_resources(priv, &priv->dma_conf);
@ -7219,10 +7220,10 @@ int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags)
static void stmmac_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 tx_cnt = priv->plat->tx_queues_to_use;
u32 rx_cnt = priv->plat->rx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
u8 rx_cnt = priv->plat->rx_queues_to_use;
unsigned int start;
int q;
u8 q;
for (q = 0; q < tx_cnt; q++) {
struct stmmac_txq_stats *txq_stats = &priv->xstats.txq_stats[q];
@ -7401,7 +7402,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
/* TXCOE doesn't work in thresh DMA mode */
if (priv->plat->force_thresh_dma_mode)
priv->plat->tx_coe = 0;
priv->plat->tx_coe = false;
else
priv->plat->tx_coe = priv->dma_cap.tx_coe;
@ -7511,7 +7512,7 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
static void stmmac_napi_add(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 queue, maxq;
u8 queue, maxq;
maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
@ -7540,7 +7541,7 @@ static void stmmac_napi_add(struct net_device *dev)
static void stmmac_napi_del(struct net_device *dev)
{
struct stmmac_priv *priv = netdev_priv(dev);
u32 queue, maxq;
u8 queue, maxq;
maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
@ -7558,7 +7559,7 @@ static void stmmac_napi_del(struct net_device *dev)
}
}
int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
int stmmac_reinit_queues(struct net_device *dev, u8 rx_cnt, u8 tx_cnt)
{
struct stmmac_priv *priv = netdev_priv(dev);
int ret = 0, i;
@ -7730,6 +7731,8 @@ struct plat_stmmacenet_data *stmmac_plat_dat_alloc(struct device *dev)
if (!plat_dat)
return NULL;
plat_dat->dma_cfg = &plat_dat->__dma_cfg;
/* Set the defaults:
* - phy autodetection
* - determine GMII_Address CR field from CSR clock
@ -7761,8 +7764,8 @@ static int __stmmac_dvr_probe(struct device *device,
{
struct net_device *ndev = NULL;
struct stmmac_priv *priv;
u32 rxq;
int i, ret = 0;
u8 rxq;
if (!plat_dat->dma_cfg || !plat_dat->dma_cfg->pbl) {
dev_err(device, "invalid DMA configuration\n");
@ -8145,7 +8148,7 @@ int stmmac_suspend(struct device *dev)
{
struct net_device *ndev = dev_get_drvdata(dev);
struct stmmac_priv *priv = netdev_priv(ndev);
u32 chan;
u8 chan;
if (!ndev || !netif_running(ndev))
goto suspend_bsp;
@ -8220,9 +8223,9 @@ static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
*/
static void stmmac_reset_queues_param(struct stmmac_priv *priv)
{
u32 rx_cnt = priv->plat->rx_queues_to_use;
u32 tx_cnt = priv->plat->tx_queues_to_use;
u32 queue;
u8 rx_cnt = priv->plat->rx_queues_to_use;
u8 tx_cnt = priv->plat->tx_queues_to_use;
u8 queue;
for (queue = 0; queue < rx_cnt; queue++)
stmmac_reset_rx_queue(priv, queue);

11
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
View File

@ -25,7 +25,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
plat->clk_csr = STMMAC_CSR_20_35M;
plat->core_type = DWMAC_CORE_GMAC;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
plat->mdio_bus_data->needs_reset = true;
}
@ -58,9 +58,9 @@ static int snps_gmac5_default_data(struct pci_dev *pdev,
plat->clk_csr = STMMAC_CSR_250_300M;
plat->core_type = DWMAC_CORE_GMAC4;
plat->force_sf_dma_mode = 1;
plat->force_sf_dma_mode = true;
plat->flags |= STMMAC_FLAG_TSO_EN;
plat->pmt = 1;
plat->pmt = true;
/* Set default number of RX and TX queues to use */
plat->tx_queues_to_use = 4;
@ -134,11 +134,6 @@ static int stmmac_pci_probe(struct pci_dev *pdev,
if (!plat->mdio_bus_data)
return -ENOMEM;
plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
GFP_KERNEL);
if (!plat->dma_cfg)
return -ENOMEM;
plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
sizeof(*plat->safety_feat_cfg),
GFP_KERNEL);

43
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
View File

@ -138,6 +138,7 @@ static int stmmac_mtl_setup(struct platform_device *pdev,
struct device_node *tx_node;
u8 queue = 0;
int ret = 0;
u32 value;
/* First Queue must always be in DCB mode. As MTL_QUEUE_DCB = 1 we need
* to always set this, otherwise Queue will be classified as AVB
@ -157,8 +158,11 @@ static int stmmac_mtl_setup(struct platform_device *pdev,
}
/* Processing RX queues common config */
of_property_read_u32(rx_node, "snps,rx-queues-to-use",
&plat->rx_queues_to_use);
if (!of_property_read_u32(rx_node, "snps,rx-queues-to-use", &value)) {
if (value > U8_MAX)
value = U8_MAX;
plat->rx_queues_to_use = value;
}
if (of_property_read_bool(rx_node, "snps,rx-sched-sp"))
plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
@ -208,8 +212,11 @@ static int stmmac_mtl_setup(struct platform_device *pdev,
}
/* Processing TX queues common config */
of_property_read_u32(tx_node, "snps,tx-queues-to-use",
&plat->tx_queues_to_use);
if (!of_property_read_u32(tx_node, "snps,tx-queues-to-use", &value)) {
if (value > U8_MAX)
value = U8_MAX;
plat->tx_queues_to_use = value;
}
if (of_property_read_bool(tx_node, "snps,tx-sched-wrr"))
plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
@ -514,47 +521,41 @@ stmmac_probe_config_dt(struct platform_device *pdev, u8 *mac)
plat->multicast_filter_bins = dwmac1000_validate_mcast_bins(
&pdev->dev, plat->multicast_filter_bins);
plat->core_type = DWMAC_CORE_GMAC;
plat->pmt = 1;
plat->pmt = true;
}
if (of_device_is_compatible(np, "snps,dwmac-3.40a")) {
plat->core_type = DWMAC_CORE_GMAC;
plat->enh_desc = 1;
plat->tx_coe = 1;
plat->bugged_jumbo = 1;
plat->pmt = 1;
plat->enh_desc = true;
plat->tx_coe = true;
plat->bugged_jumbo = true;
plat->pmt = true;
}
if (of_device_compatible_match(np, stmmac_gmac4_compats)) {
plat->core_type = DWMAC_CORE_GMAC4;
plat->pmt = 1;
plat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat->flags |= STMMAC_FLAG_TSO_EN;
}
if (of_device_is_compatible(np, "snps,dwmac-3.610") ||
of_device_is_compatible(np, "snps,dwmac-3.710")) {
plat->enh_desc = 1;
plat->bugged_jumbo = 1;
plat->force_sf_dma_mode = 1;
plat->enh_desc = true;
plat->bugged_jumbo = true;
plat->force_sf_dma_mode = true;
}
if (of_device_is_compatible(np, "snps,dwxgmac")) {
plat->core_type = DWMAC_CORE_XGMAC;
plat->pmt = 1;
plat->pmt = true;
if (of_property_read_bool(np, "snps,tso"))
plat->flags |= STMMAC_FLAG_TSO_EN;
of_property_read_u32(np, "snps,multicast-filter-bins",
&plat->multicast_filter_bins);
}
dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
GFP_KERNEL);
if (!dma_cfg) {
ret = ERR_PTR(-ENOMEM);
goto error_put_mdio;
}
plat->dma_cfg = dma_cfg;
dma_cfg = plat->dma_cfg;
of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
if (!dma_cfg->pbl)

95
include/linux/stmmac.h
View File

@ -93,52 +93,73 @@ struct stmmac_mdio_bus_data {
};
struct stmmac_dma_cfg {
/* pbl: programmable burst limit
* txpbl: transmit programmable burst limit
* rxpbl: receive programmable burst limit
* If txpbl or rxpbl are zero, the value of pbl will be substituted.
* Range 0 - 63.
*/
int pbl;
int txpbl;
int rxpbl;
/* pblx8: multiplies pbl, txpbl, rxpbl by a factor of 8 for dwmac >=
* 3.50a, or a factor of 4 for previous versions.
*/
bool pblx8;
/* fixed_burst:
* when set, AXI bursts defined by axi_blen_regval are permitted.
* AHB uses SINGLE, INCR4, INCR8 or INCR16 during burst transfers.
* when clear, AXI and AHB use SINGLE or INCR bursts.
*/
bool fixed_burst;
/* mixed_burst:
* when set and fixed_burst is clear, AHB uses INCR for bursts > 16
* and SINGLE or INCRx for bursts <= 16.
*/
bool mixed_burst;
/* aal: address aligned bursts for AHB and AXI master interface */
bool aal;
bool eame;
bool multi_msi_en;
bool dche;
bool eame;
/* multi_msi_en: stmmac core internal */
bool multi_msi_en;
/* atds: stmmac core internal */
bool atds;
};
#define AXI_BLEN 7
struct stmmac_axi {
bool axi_lpi_en;
bool axi_xit_frm;
u32 axi_wr_osr_lmt;
u32 axi_rd_osr_lmt;
bool axi_kbbe;
u32 axi_blen_regval;
bool axi_lpi_en;
bool axi_xit_frm;
bool axi_kbbe;
bool axi_fb;
bool axi_mb;
bool axi_rb;
};
struct stmmac_rxq_cfg {
u8 mode_to_use;
u32 chan;
u32 prio;
u8 mode_to_use;
u8 pkt_route;
bool use_prio;
u32 prio;
};
struct stmmac_txq_cfg {
u32 weight;
bool coe_unsupported;
u8 mode_to_use;
/* Credit Base Shaper parameters */
u32 send_slope;
u32 idle_slope;
u32 high_credit;
u32 low_credit;
bool use_prio;
u32 prio;
int tbs_en;
bool use_prio;
bool coe_unsupported;
u8 mode_to_use;
};
struct stmmac_safety_feature_cfg {
@ -229,23 +250,23 @@ struct plat_stmmacenet_data {
struct stmmac_dma_cfg *dma_cfg;
struct stmmac_safety_feature_cfg *safety_feat_cfg;
int clk_csr;
int enh_desc;
int tx_coe;
bool enh_desc;
bool tx_coe;
bool bugged_jumbo;
bool pmt;
bool force_sf_dma_mode;
bool force_thresh_dma_mode;
bool riwt_off;
int rx_coe;
int bugged_jumbo;
int pmt;
int force_sf_dma_mode;
int force_thresh_dma_mode;
int riwt_off;
int max_speed;
int maxmtu;
int multicast_filter_bins;
int unicast_filter_entries;
int tx_fifo_size;
int rx_fifo_size;
u32 host_dma_width;
u32 rx_queues_to_use;
u32 tx_queues_to_use;
u8 host_dma_width;
u8 rx_queues_to_use;
u8 tx_queues_to_use;
u8 rx_sched_algorithm;
u8 tx_sched_algorithm;
struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
@ -279,10 +300,41 @@ struct plat_stmmacenet_data {
struct phylink_pcs *(*select_pcs)(struct stmmac_priv *priv,
phy_interface_t interface);
void *bsp_priv;
/* stmmac clocks:
* stmmac_clk: CSR clock (which can be hclk_i, clk_csr_i, aclk_i,
* or clk_app_i depending on GMAC configuration). This clock
* generates the MDC clock.
*
* pclk: introduced for Imagination Technologies Pistachio board -
* see 5f9755d26fbf ("stmmac: Add an optional register interface
* clock"). This is probably used for cases where separate clocks
* are provided for the host interface and register interface. In
* this case, as the MDC clock is derived from stmmac_clk, pclk
* can only really be the "application clock" for the "host
* interface" and not the "register interface" aka CSR clock as
* it is never used when determining the divider for the MDC
* clock.
*
* clk_ptp_ref: optional PTP reference clock (clk_ptp_ref_i). When
* present, this clock increments the timestamp value. Otherwise,
* the rate of stmmac_clk will be used.
*
* clk_tx_i: MAC transmit clock, which will be 2.5MHz for 10M,
* 25MHz for 100M, or 125MHz for 1G irrespective of the interface
* mode. For the DWMAC PHY interface modes:
*
* GMII/MII PHY's transmit clock for 10M (2.5MHz) or 100M (25MHz),
* or 125MHz local clock for 1G mode
* RMII 50MHz RMII clock divided by 2 or 20.
* RGMII 125MHz local clock divided by 1, 5, or 50.
* SGMII 125MHz SerDes clock divided by 1, 5, or 50.
* TBI/RTBI 125MHz SerDes clock
*/
struct clk *stmmac_clk;
struct clk *pclk;
struct clk *clk_ptp_ref;
struct clk *clk_tx_i; /* clk_tx_i to MAC core */
struct clk *clk_tx_i;
unsigned long clk_ptp_rate;
unsigned long clk_ref_rate;
struct clk_bulk_data *clks;
@ -306,5 +358,6 @@ struct plat_stmmacenet_data {
int msi_tx_base_vec;
const struct dwmac4_addrs *dwmac4_addrs;
unsigned int flags;
struct stmmac_dma_cfg __dma_cfg;
};
#endif