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drm/i915/bw: relocate intel_can_enable_sagv() and rename to intel_bw_can_enable_sagv()

Browse Source 
Prefer only looking at struct intel_bw_state internals inside
intel_bw.c. To that effect, move intel_can_enable_sagv() there, and
rename to intel_bw_can_enable_sagv() to have consistent naming.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/dd6e3857bd1343c07a36826e99c1c04f7dd5ddb5.1750847509.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
This commit is contained in:
Jani Nikula 2025-06-25 13:32:23 +03:00
parent e17643d075
commit 4822cb81a7
4 changed files with 21 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
drivers/gpu/drm/i915/display/intel_bw.c
View File

@ -1001,7 +1001,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
* for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
* not enabled. PM Demand code will clamp the value for the register
*/
if (!intel_can_enable_sagv(display, new_bw_state)) {
if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
new_bw_state->qgv_point_peakbw = U16_MAX;
drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");
return 0;
@ -1114,7 +1114,7 @@ static int icl_find_qgv_points(struct intel_display *display,
* we can't enable SAGV due to the increased memory latency it may
* cause.
*/
if (!intel_can_enable_sagv(display, new_bw_state)) {
if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);
drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",
qgv_points);
@ -1481,8 +1481,8 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
if (!new_bw_state)
return 0;
if (intel_can_enable_sagv(display, new_bw_state) !=
intel_can_enable_sagv(display, old_bw_state)) {
if (intel_bw_can_enable_sagv(display, new_bw_state) !=
intel_bw_can_enable_sagv(display, old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
return ret;
@ -1528,8 +1528,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)
new_bw_state = intel_atomic_get_new_bw_state(state);
if (new_bw_state &&
intel_can_enable_sagv(display, old_bw_state) !=
intel_can_enable_sagv(display, new_bw_state))
intel_bw_can_enable_sagv(display, old_bw_state) !=
intel_bw_can_enable_sagv(display, new_bw_state))
changed = true;
/*
@ -1665,3 +1665,13 @@ bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
return false;
}
bool intel_bw_can_enable_sagv(struct intel_display *display,
const struct intel_bw_state *bw_state)
{
if (DISPLAY_VER(display) < 11 &&
bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
return false;
return bw_state->pipe_sagv_reject == 0;
}

2
drivers/gpu/drm/i915/display/intel_bw.h
View File

@ -77,5 +77,7 @@ void intel_bw_update_hw_state(struct intel_display *display);
void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
bool intel_bw_can_enable_sagv(struct intel_display *display,
const struct intel_bw_state *bw_state);
#endif /* __INTEL_BW_H__ */

16
drivers/gpu/drm/i915/display/skl_watermark.c
View File

@ -248,7 +248,7 @@ static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
if (!intel_can_enable_sagv(display, new_bw_state))
if (!intel_bw_can_enable_sagv(display, new_bw_state))
skl_sagv_disable(display);
}
@ -261,7 +261,7 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
if (intel_can_enable_sagv(display, new_bw_state))
if (intel_bw_can_enable_sagv(display, new_bw_state))
skl_sagv_enable(display);
}
@ -462,16 +462,6 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return skl_crtc_can_enable_sagv(crtc_state);
}
bool intel_can_enable_sagv(struct intel_display *display,
const struct intel_bw_state *bw_state)
{
if (DISPLAY_VER(display) < 11 &&
bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
return false;
return bw_state->pipe_sagv_reject == 0;
}
static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
u16 start, u16 end)
{
@ -3035,7 +3025,7 @@ skl_compute_wm(struct intel_atomic_state *state)
* drm_atomic_check_only() gets upset if we pull more crtcs
* into the state, so we have to calculate this based on the
* individual intel_crtc_can_enable_sagv() rather than
* the overall intel_can_enable_sagv(). Otherwise the
* the overall intel_bw_can_enable_sagv(). Otherwise the
* crtcs not included in the commit would not switch to the
* SAGV watermarks when we are about to enable SAGV, and that
* would lead to underruns. This does mean extra power draw

3
drivers/gpu/drm/i915/display/skl_watermark.h
View File

@ -10,7 +10,6 @@
enum plane_id;
struct intel_atomic_state;
struct intel_bw_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_dbuf_state;
@ -26,8 +25,6 @@ u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
bool intel_can_enable_sagv(struct intel_display *display,
const struct intel_bw_state *bw_state);
bool intel_has_sagv(struct intel_display *display);
u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,