From a9d9bfcadfb43b856dbcf9419de75f7420d5a225 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Mon, 11 Jan 2021 03:12:43 +0100 Subject: [PATCH 1/5] arm64: dts: armada-3720-turris-mox: rename u-boot mtd partition to a53-firmware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The partition called "u-boot" in reality contains TF-A and U-Boot, and TF-A is before U-Boot. Rename this parition to "a53-firmware" to avoid confusion for users, since they cannot simply build U-Boot from U-Boot repository and flash the resulting image there. Instead they have to build the firmware with the sources from the mox-boot-builder repository [1] and flash the a53-firmware.bin binary there. [1] https://gitlab.nic.cz/turris/mox-boot-builder Signed-off-by: Marek Behún Fixes: 7109d817db2e ("arm64: dts: marvell: add DTS for Turris Mox") Cc: Gregory CLEMENT Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index f5ec3b644769..d239ab70ed99 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -205,7 +205,7 @@ partition@0 { }; partition@20000 { - label = "u-boot"; + label = "a53-firmware"; reg = <0x20000 0x160000>; }; From 6c55091335213faf42eaf4c17614cc15ef70e735 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Tue, 12 Jan 2021 11:46:54 +0200 Subject: [PATCH 2/5] arm64: dts: change AP807 SDHCI compatibility string This patch adds new compatible string to AP807 DTSI to avoid its SDHCI controller to run in "slow mode" with disabled UHS. Signed-off-by: Marcin Wojtas Signed-off-by: Konstantin Porotchkin Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi index 623010f3ca89..d9bbbfa4b4eb 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi @@ -27,3 +27,8 @@ cpu_clk: clock-cpu { #clock-cells = <1>; }; }; + +&ap_sdhci0 { + compatible = "marvell,armada-ap807-sdhci"; +}; + From e8ff9d5996ac865982319cd44be9cf0515d31f82 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Tue, 12 Jan 2021 11:46:55 +0200 Subject: [PATCH 3/5] arm64: dts: cn913x-db: enable MMC HS400 This patch adds necessary flags in the device tree which enable HS400 mode on AP807 MMC controller on the CN913x-DB board. Signed-off-by: Marcin Wojtas Signed-off-by: Konstantin Porotchkin Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/cn9130-db.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts index ce49a70d88a0..79020e6d2792 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dts +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts @@ -113,6 +113,8 @@ &uart0 { &ap_sdhci0 { pinctrl-names = "default"; bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs400-1_8v; vqmmc-supply = <&ap0_reg_sd_vccq>; status = "okay"; }; From 6ece0f7dbd558670ec72ba390379949a4d4dc5c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Mon, 18 Jan 2021 10:31:39 +0100 Subject: [PATCH 4/5] arm64: dts: marvell: armada-37xx: Add SATA comphy into main armada-37xx.dtsi file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SATA on A3720 SOC can use only comphy2, so move this definition from board specific DTS file armada-3720-espressobin.dtsi into main A3720 SOC file armada-37xx.dtsi. Signed-off-by: Pali Rohár Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi | 2 -- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi index daffe136c523..5fc613d24151 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi @@ -67,8 +67,6 @@ &pcie0 { /* J6 */ &sata { status = "okay"; - phys = <&comphy2 0>; - phy-names = "sata-phy"; }; /* U11 */ diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index d5b6c0a1c54a..7a2df148c6a3 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -458,6 +458,8 @@ sata: sata@e0000 { reg = <0xe0000 0x178>; interrupts = ; clocks = <&nb_periph_clk 1>; + phys = <&comphy2 0>; + phy-names = "sata-phy"; status = "disabled"; }; From 35db5e32ebc16330ae6275c24783efa4091af1bc Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 11 Jan 2021 13:46:28 +0200 Subject: [PATCH 5/5] arm64: dts: armada: add pwm offsets for ap/cp gpios The 'marvell,pwm-offset' property of both GPIO blocks (per CP component) point to the same counter registers offset. The driver will decide how to use counters A/B. This is different from the convention of pwm on earlier Armada series (370/38x). On those systems the assignment of A/B counters to GPIO blocks is coded in both DT and the driver. The actual behaviour of the current driver on Armada 8K/7K is the same as earlier systems. Add also clock properties for base pwm frequency reference. Signed-off-by: Baruch Siach Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 3 +++ arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 12e477f1aeb9..6614472100c2 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -281,6 +281,9 @@ ap_gpio: gpio@1040 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&ap_pinctrl 0 0 20>; + marvell,pwm-offset = <0x10c0>; + #pwm-cells = <2>; + clocks = <&ap_clk 3>; }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 994a2fce449a..d774a39334d9 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -234,12 +234,17 @@ CP11X_LABEL(gpio1): gpio@100 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>; + marvell,pwm-offset = <0x1f0>; + #pwm-cells = <2>; interrupt-controller; interrupts = <86 IRQ_TYPE_LEVEL_HIGH>, <85 IRQ_TYPE_LEVEL_HIGH>, <84 IRQ_TYPE_LEVEL_HIGH>, <83 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; + clock-names = "core", "axi"; + clocks = <&CP11X_LABEL(clk) 1 21>, + <&CP11X_LABEL(clk) 1 17>; status = "disabled"; }; @@ -250,12 +255,17 @@ CP11X_LABEL(gpio2): gpio@140 { gpio-controller; #gpio-cells = <2>; gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>; + marvell,pwm-offset = <0x1f0>; + #pwm-cells = <2>; interrupt-controller; interrupts = <82 IRQ_TYPE_LEVEL_HIGH>, <81 IRQ_TYPE_LEVEL_HIGH>, <80 IRQ_TYPE_LEVEL_HIGH>, <79 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; + clock-names = "core", "axi"; + clocks = <&CP11X_LABEL(clk) 1 21>, + <&CP11X_LABEL(clk) 1 17>; status = "disabled"; }; };