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PM / devfreq: rockchip_dmc: add support for rk3328
This adds the necessary data for handling dmcfreq on the rk3328 Change-Id: If4cff5cc372f80b6776a7272a1bff54abef2cf33 Signed-off-by: CanYang He <hcy@rock-chips.com>
This commit is contained in:
Hecanyang
Tao Huang
parent
3397fb4994
commit
4807c45f72
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@ -4,6 +4,7 @@ Required properties:
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- compatible: Should be one of the following.
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- "rockchip,rk3128-dmc" - for RK3128 SoCs.
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- "rockchip,rk3288-dmc" - for RK3288 SoCs.
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- "rockchip,rk3328-dmc" - for RK3328 SoCs.
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- "rockchip,rk3368-dmc" - for RK3368 SoCs.
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- "rockchip,rk3399-dmc" - for RK3399 SoCs.
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- devfreq-events: Node to get DDR loading, Refer to
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@ -255,6 +255,8 @@ static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
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p->hz = drate;
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p->lcdc_type = rk_drm_get_lcdc_type();
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p->wait_flag1 = 1;
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p->wait_flag0 = 1;
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res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE);
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@ -322,15 +322,15 @@ static struct rockchip_clk_branch rk3328_clk_branches[] __initdata = {
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RK3328_CLKGATE_CON(14), 1, GFLAGS),
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/* PD_DDR */
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COMPOSITE(0, "clk_ddr_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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RK3328_CLKSEL_CON(3), 8, 2, MFLAGS, 0, 3, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
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RK3328_CLKGATE_CON(0), 4, GFLAGS),
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FACTOR(0, "clk_ddr", "clk_ddr_src", 0, 1, 2),
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GATE(0, "clk_ddrmsch", "clk_ddr", CLK_IGNORE_UNUSED,
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COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
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RK3328_CLKSEL_CON(3), 8, 2, 0, 3,
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ROCKCHIP_DDRCLK_SIP_V2),
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GATE(0, "clk_ddrmsch", "sclk_ddrc", CLK_IGNORE_UNUSED,
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RK3328_CLKGATE_CON(18), 6, GFLAGS),
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GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
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GATE(0, "clk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
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RK3328_CLKGATE_CON(18), 5, GFLAGS),
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GATE(0, "aclk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
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GATE(0, "aclk_ddrupctl", "sclk_ddrc", CLK_IGNORE_UNUSED,
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RK3328_CLKGATE_CON(18), 4, GFLAGS),
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GATE(0, "clk_ddrmon", "xin24m", CLK_IGNORE_UNUSED,
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RK3328_CLKGATE_CON(0), 6, GFLAGS),
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@ -99,7 +99,7 @@ struct share_params {
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static struct share_params *ddr_psci_param;
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static const char *rk3128_dts_timing[] = {
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static const char * const rk3128_dts_timing[] = {
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"ddr3_speed_bin",
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"pd_idle",
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"sr_idle",
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@ -146,7 +146,7 @@ struct rk3128_ddr_dts_config_timing {
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u32 available;
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};
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char *rk3288_dts_timing[] = {
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static const char * const rk3288_dts_timing[] = {
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"ddr3_speed_bin",
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"pd_idle",
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"sr_idle",
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@ -206,6 +206,340 @@ struct rk3288_ddr_dts_config_timing {
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unsigned int available;
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};
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/* hope this define can adapt all future platfor */
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static const char * const rk3328_dts_timing[] = {
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"ddr3_speed_bin",
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"ddr4_speed_bin",
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"pd_idle",
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"sr_idle",
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"sr_mc_gate_idle",
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"srpd_lite_idle",
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"standby_idle",
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"auto_pd_dis_freq",
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"auto_sr_dis_freq",
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"ddr3_dll_dis_freq",
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"ddr4_dll_dis_freq",
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"phy_dll_dis_freq",
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"ddr3_odt_dis_freq",
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"phy_ddr3_odt_dis_freq",
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"ddr3_drv",
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"ddr3_odt",
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"phy_ddr3_ca_drv",
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"phy_ddr3_ck_drv",
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"phy_ddr3_dq_drv",
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"phy_ddr3_odt",
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"lpddr3_odt_dis_freq",
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"phy_lpddr3_odt_dis_freq",
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"lpddr3_drv",
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"lpddr3_odt",
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"phy_lpddr3_ca_drv",
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"phy_lpddr3_ck_drv",
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"phy_lpddr3_dq_drv",
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"phy_lpddr3_odt",
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"lpddr4_odt_dis_freq",
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"phy_lpddr4_odt_dis_freq",
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"lpddr4_drv",
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"lpddr4_dq_odt",
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"lpddr4_ca_odt",
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"phy_lpddr4_ca_drv",
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"phy_lpddr4_ck_cs_drv",
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"phy_lpddr4_dq_drv",
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"phy_lpddr4_odt",
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"ddr4_odt_dis_freq",
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"phy_ddr4_odt_dis_freq",
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"ddr4_drv",
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"ddr4_odt",
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"phy_ddr4_ca_drv",
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"phy_ddr4_ck_drv",
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"phy_ddr4_dq_drv",
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"phy_ddr4_odt",
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};
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static const char * const rk3328_dts_ca_timing[] = {
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"ddr3a1_ddr4a9_de-skew",
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"ddr3a0_ddr4a10_de-skew",
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"ddr3a3_ddr4a6_de-skew",
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"ddr3a2_ddr4a4_de-skew",
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"ddr3a5_ddr4a8_de-skew",
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"ddr3a4_ddr4a5_de-skew",
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"ddr3a7_ddr4a11_de-skew",
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"ddr3a6_ddr4a7_de-skew",
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"ddr3a9_ddr4a0_de-skew",
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"ddr3a8_ddr4a13_de-skew",
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"ddr3a11_ddr4a3_de-skew",
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"ddr3a10_ddr4cs0_de-skew",
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"ddr3a13_ddr4a2_de-skew",
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"ddr3a12_ddr4ba1_de-skew",
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"ddr3a15_ddr4odt0_de-skew",
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"ddr3a14_ddr4a1_de-skew",
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"ddr3ba1_ddr4a15_de-skew",
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"ddr3ba0_ddr4bg0_de-skew",
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"ddr3ras_ddr4cke_de-skew",
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"ddr3ba2_ddr4ba0_de-skew",
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"ddr3we_ddr4bg1_de-skew",
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"ddr3cas_ddr4a12_de-skew",
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"ddr3ckn_ddr4ckn_de-skew",
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"ddr3ckp_ddr4ckp_de-skew",
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"ddr3cke_ddr4a16_de-skew",
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"ddr3odt0_ddr4a14_de-skew",
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"ddr3cs0_ddr4act_de-skew",
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"ddr3reset_ddr4reset_de-skew",
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"ddr3cs1_ddr4cs1_de-skew",
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"ddr3odt1_ddr4odt1_de-skew",
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};
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static const char * const rk3328_dts_cs0_timing[] = {
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"cs0_dm0_rx_de-skew",
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"cs0_dm0_tx_de-skew",
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"cs0_dq0_rx_de-skew",
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"cs0_dq0_tx_de-skew",
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"cs0_dq1_rx_de-skew",
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"cs0_dq1_tx_de-skew",
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"cs0_dq2_rx_de-skew",
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"cs0_dq2_tx_de-skew",
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"cs0_dq3_rx_de-skew",
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"cs0_dq3_tx_de-skew",
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"cs0_dq4_rx_de-skew",
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"cs0_dq4_tx_de-skew",
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"cs0_dq5_rx_de-skew",
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"cs0_dq5_tx_de-skew",
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"cs0_dq6_rx_de-skew",
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"cs0_dq6_tx_de-skew",
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"cs0_dq7_rx_de-skew",
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"cs0_dq7_tx_de-skew",
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"cs0_dqs0_rx_de-skew",
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"cs0_dqs0p_tx_de-skew",
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"cs0_dqs0n_tx_de-skew",
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"cs0_dm1_rx_de-skew",
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"cs0_dm1_tx_de-skew",
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"cs0_dq8_rx_de-skew",
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"cs0_dq8_tx_de-skew",
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"cs0_dq9_rx_de-skew",
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"cs0_dq9_tx_de-skew",
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"cs0_dq10_rx_de-skew",
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"cs0_dq10_tx_de-skew",
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"cs0_dq11_rx_de-skew",
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"cs0_dq11_tx_de-skew",
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"cs0_dq12_rx_de-skew",
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"cs0_dq12_tx_de-skew",
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"cs0_dq13_rx_de-skew",
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"cs0_dq13_tx_de-skew",
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"cs0_dq14_rx_de-skew",
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"cs0_dq14_tx_de-skew",
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"cs0_dq15_rx_de-skew",
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"cs0_dq15_tx_de-skew",
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"cs0_dqs1_rx_de-skew",
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"cs0_dqs1p_tx_de-skew",
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"cs0_dqs1n_tx_de-skew",
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"cs0_dm2_rx_de-skew",
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"cs0_dm2_tx_de-skew",
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"cs0_dq16_rx_de-skew",
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"cs0_dq16_tx_de-skew",
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"cs0_dq17_rx_de-skew",
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"cs0_dq17_tx_de-skew",
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"cs0_dq18_rx_de-skew",
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"cs0_dq18_tx_de-skew",
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"cs0_dq19_rx_de-skew",
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"cs0_dq19_tx_de-skew",
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"cs0_dq20_rx_de-skew",
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"cs0_dq20_tx_de-skew",
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"cs0_dq21_rx_de-skew",
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"cs0_dq21_tx_de-skew",
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"cs0_dq22_rx_de-skew",
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"cs0_dq22_tx_de-skew",
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"cs0_dq23_rx_de-skew",
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"cs0_dq23_tx_de-skew",
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"cs0_dqs2_rx_de-skew",
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"cs0_dqs2p_tx_de-skew",
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"cs0_dqs2n_tx_de-skew",
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"cs0_dm3_rx_de-skew",
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"cs0_dm3_tx_de-skew",
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"cs0_dq24_rx_de-skew",
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"cs0_dq24_tx_de-skew",
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"cs0_dq25_rx_de-skew",
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"cs0_dq25_tx_de-skew",
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"cs0_dq26_rx_de-skew",
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"cs0_dq26_tx_de-skew",
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"cs0_dq27_rx_de-skew",
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"cs0_dq27_tx_de-skew",
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"cs0_dq28_rx_de-skew",
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"cs0_dq28_tx_de-skew",
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"cs0_dq29_rx_de-skew",
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"cs0_dq29_tx_de-skew",
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"cs0_dq30_rx_de-skew",
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"cs0_dq30_tx_de-skew",
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"cs0_dq31_rx_de-skew",
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"cs0_dq31_tx_de-skew",
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"cs0_dqs3_rx_de-skew",
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"cs0_dqs3p_tx_de-skew",
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"cs0_dqs3n_tx_de-skew",
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};
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static const char * const rk3328_dts_cs1_timing[] = {
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"cs1_dm0_rx_de-skew",
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"cs1_dm0_tx_de-skew",
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"cs1_dq0_rx_de-skew",
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"cs1_dq0_tx_de-skew",
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"cs1_dq1_rx_de-skew",
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"cs1_dq1_tx_de-skew",
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"cs1_dq2_rx_de-skew",
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"cs1_dq2_tx_de-skew",
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"cs1_dq3_rx_de-skew",
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"cs1_dq3_tx_de-skew",
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"cs1_dq4_rx_de-skew",
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"cs1_dq4_tx_de-skew",
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"cs1_dq5_rx_de-skew",
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"cs1_dq5_tx_de-skew",
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"cs1_dq6_rx_de-skew",
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"cs1_dq6_tx_de-skew",
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"cs1_dq7_rx_de-skew",
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"cs1_dq7_tx_de-skew",
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"cs1_dqs0_rx_de-skew",
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"cs1_dqs0p_tx_de-skew",
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"cs1_dqs0n_tx_de-skew",
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"cs1_dm1_rx_de-skew",
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"cs1_dm1_tx_de-skew",
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"cs1_dq8_rx_de-skew",
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"cs1_dq8_tx_de-skew",
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"cs1_dq9_rx_de-skew",
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"cs1_dq9_tx_de-skew",
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"cs1_dq10_rx_de-skew",
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"cs1_dq10_tx_de-skew",
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"cs1_dq11_rx_de-skew",
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"cs1_dq11_tx_de-skew",
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"cs1_dq12_rx_de-skew",
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"cs1_dq12_tx_de-skew",
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"cs1_dq13_rx_de-skew",
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"cs1_dq13_tx_de-skew",
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"cs1_dq14_rx_de-skew",
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"cs1_dq14_tx_de-skew",
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"cs1_dq15_rx_de-skew",
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"cs1_dq15_tx_de-skew",
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"cs1_dqs1_rx_de-skew",
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"cs1_dqs1p_tx_de-skew",
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"cs1_dqs1n_tx_de-skew",
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"cs1_dm2_rx_de-skew",
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"cs1_dm2_tx_de-skew",
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"cs1_dq16_rx_de-skew",
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"cs1_dq16_tx_de-skew",
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"cs1_dq17_rx_de-skew",
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"cs1_dq17_tx_de-skew",
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"cs1_dq18_rx_de-skew",
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"cs1_dq18_tx_de-skew",
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"cs1_dq19_rx_de-skew",
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"cs1_dq19_tx_de-skew",
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"cs1_dq20_rx_de-skew",
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"cs1_dq20_tx_de-skew",
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"cs1_dq21_rx_de-skew",
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"cs1_dq21_tx_de-skew",
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"cs1_dq22_rx_de-skew",
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"cs1_dq22_tx_de-skew",
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"cs1_dq23_rx_de-skew",
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"cs1_dq23_tx_de-skew",
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"cs1_dqs2_rx_de-skew",
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"cs1_dqs2p_tx_de-skew",
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"cs1_dqs2n_tx_de-skew",
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"cs1_dm3_rx_de-skew",
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"cs1_dm3_tx_de-skew",
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"cs1_dq24_rx_de-skew",
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"cs1_dq24_tx_de-skew",
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"cs1_dq25_rx_de-skew",
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"cs1_dq25_tx_de-skew",
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"cs1_dq26_rx_de-skew",
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"cs1_dq26_tx_de-skew",
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"cs1_dq27_rx_de-skew",
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"cs1_dq27_tx_de-skew",
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"cs1_dq28_rx_de-skew",
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"cs1_dq28_tx_de-skew",
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"cs1_dq29_rx_de-skew",
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"cs1_dq29_tx_de-skew",
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"cs1_dq30_rx_de-skew",
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"cs1_dq30_tx_de-skew",
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"cs1_dq31_rx_de-skew",
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"cs1_dq31_tx_de-skew",
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"cs1_dqs3_rx_de-skew",
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"cs1_dqs3p_tx_de-skew",
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"cs1_dqs3n_tx_de-skew",
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};
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struct rk3328_ddr_dts_config_timing {
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unsigned int ddr3_speed_bin;
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unsigned int ddr4_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int auto_sr_dis_freq;
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/* for ddr3 only */
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unsigned int ddr3_dll_dis_freq;
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/* for ddr4 only */
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unsigned int ddr4_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr3_odt_dis_freq;
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unsigned int phy_ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_ck_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int phy_lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
|
||||
unsigned int phy_lpddr3_ck_drv;
|
||||
unsigned int phy_lpddr3_dq_drv;
|
||||
unsigned int phy_lpddr3_odt;
|
||||
|
||||
unsigned int lpddr4_odt_dis_freq;
|
||||
unsigned int phy_lpddr4_odt_dis_freq;
|
||||
unsigned int lpddr4_drv;
|
||||
unsigned int lpddr4_dq_odt;
|
||||
unsigned int lpddr4_ca_odt;
|
||||
unsigned int phy_lpddr4_ca_drv;
|
||||
unsigned int phy_lpddr4_ck_cs_drv;
|
||||
unsigned int phy_lpddr4_dq_drv;
|
||||
unsigned int phy_lpddr4_odt;
|
||||
|
||||
unsigned int ddr4_odt_dis_freq;
|
||||
unsigned int phy_ddr4_odt_dis_freq;
|
||||
unsigned int ddr4_drv;
|
||||
unsigned int ddr4_odt;
|
||||
unsigned int phy_ddr4_ca_drv;
|
||||
unsigned int phy_ddr4_ck_drv;
|
||||
unsigned int phy_ddr4_dq_drv;
|
||||
unsigned int phy_ddr4_odt;
|
||||
|
||||
unsigned int ca_skew[15];
|
||||
unsigned int cs0_skew[44];
|
||||
unsigned int cs1_skew[44];
|
||||
|
||||
unsigned int available;
|
||||
};
|
||||
|
||||
struct rk3328_ddr_de_skew_setting {
|
||||
unsigned int ca_de_skew[30];
|
||||
unsigned int cs0_de_skew[84];
|
||||
unsigned int cs1_de_skew[84];
|
||||
};
|
||||
|
||||
struct rk3368_dram_timing {
|
||||
u32 dram_spd_bin;
|
||||
u32 sr_idle;
|
||||
|
|
@ -311,6 +645,61 @@ struct rockchip_dmcfreq {
|
|||
|
||||
static struct rockchip_dmcfreq *rk_dmcfreq;
|
||||
|
||||
/*
|
||||
* function: packaging de-skew setting to rk3328_ddr_dts_config_timing,
|
||||
* rk3328_ddr_dts_config_timing will pass to trust firmware, and
|
||||
* used direct to set register.
|
||||
* input: de_skew
|
||||
* output: tim
|
||||
*/
|
||||
static void rk3328_de_skew_setting_2_register(struct rk3328_ddr_de_skew_setting *de_skew,
|
||||
struct rk3328_ddr_dts_config_timing *tim)
|
||||
{
|
||||
u32 n;
|
||||
u32 offset;
|
||||
u32 shift;
|
||||
|
||||
memset_io(tim->ca_skew, 0, sizeof(tim->ca_skew));
|
||||
memset_io(tim->cs0_skew, 0, sizeof(tim->cs0_skew));
|
||||
memset_io(tim->cs1_skew, 0, sizeof(tim->cs1_skew));
|
||||
|
||||
/* CA de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->ca_de_skew); n++) {
|
||||
offset = n / 2;
|
||||
shift = n % 2;
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->ca_skew[offset] &= ~(0xf << shift);
|
||||
tim->ca_skew[offset] |= (de_skew->ca_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS0 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs0_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs0_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs0_skew[offset] |= (de_skew->cs0_de_skew[n] << shift);
|
||||
}
|
||||
|
||||
/* CS1 data de-skew */
|
||||
for (n = 0; n < ARRAY_SIZE(de_skew->cs1_de_skew); n++) {
|
||||
offset = ((n / 21) * 11) + ((n % 21) / 2);
|
||||
shift = ((n % 21) % 2);
|
||||
if ((n % 21) == 20)
|
||||
shift = 0;
|
||||
else
|
||||
/* 0 => 4; 1 => 0 */
|
||||
shift = (shift == 0) ? 4 : 0;
|
||||
tim->cs1_skew[offset] &= ~(0xf << shift);
|
||||
tim->cs1_skew[offset] |= (de_skew->cs1_de_skew[n] << shift);
|
||||
}
|
||||
}
|
||||
|
||||
static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
|
||||
u32 flags)
|
||||
{
|
||||
|
|
@ -320,7 +709,7 @@ static int rockchip_dmcfreq_target(struct device *dev, unsigned long *freq,
|
|||
unsigned long old_clk_rate = dmcfreq->rate;
|
||||
unsigned long temp_rate, target_volt, target_rate;
|
||||
unsigned int cpu_cur, cpufreq_cur;
|
||||
int err;
|
||||
int err = 0;
|
||||
|
||||
rcu_read_lock();
|
||||
|
||||
|
|
@ -641,6 +1030,64 @@ static void of_get_rk3288_timings(struct device *dev,
|
|||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static void of_get_rk3328_timings(struct device *dev,
|
||||
struct device_node *np, uint32_t *timing)
|
||||
{
|
||||
struct device_node *np_tim;
|
||||
u32 *p;
|
||||
struct rk3328_ddr_dts_config_timing *dts_timing;
|
||||
struct rk3328_ddr_de_skew_setting *de_skew;
|
||||
int ret = 0;
|
||||
u32 i;
|
||||
|
||||
dts_timing =
|
||||
(struct rk3328_ddr_dts_config_timing *)(timing +
|
||||
DTS_PAR_OFFSET / 4);
|
||||
|
||||
np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
|
||||
if (!np_tim) {
|
||||
ret = -EINVAL;
|
||||
goto end;
|
||||
}
|
||||
de_skew = kmalloc(sizeof(*de_skew), GFP_KERNEL);
|
||||
if (!de_skew) {
|
||||
ret = -ENOMEM;
|
||||
goto end;
|
||||
}
|
||||
p = (u32 *)dts_timing;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->ca_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_ca_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_ca_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs0_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs0_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs0_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)de_skew->cs1_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk3328_dts_cs1_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk3328_dts_cs1_timing[i],
|
||||
p + i);
|
||||
}
|
||||
if (!ret)
|
||||
rk3328_de_skew_setting_2_register(de_skew, dts_timing);
|
||||
kfree(de_skew);
|
||||
end:
|
||||
if (!ret) {
|
||||
dts_timing->available = 1;
|
||||
} else {
|
||||
dts_timing->available = 0;
|
||||
dev_err(dev, "of_get_ddr_timings: fail\n");
|
||||
}
|
||||
|
||||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
|
||||
struct device_node *np)
|
||||
{
|
||||
|
|
@ -703,6 +1150,94 @@ static struct rk3368_dram_timing *of_get_rk3368_timings(struct device *dev,
|
|||
return timing;
|
||||
}
|
||||
|
||||
static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct rk3399_dram_timing *timing = NULL;
|
||||
struct device_node *np_tim;
|
||||
int ret;
|
||||
|
||||
np_tim = of_parse_phandle(np, "ddr_timing", 0);
|
||||
if (np_tim) {
|
||||
timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
|
||||
if (!timing)
|
||||
goto err;
|
||||
|
||||
ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
|
||||
&timing->ddr3_speed_bin);
|
||||
ret |= of_property_read_u32(np_tim, "pd_idle",
|
||||
&timing->pd_idle);
|
||||
ret |= of_property_read_u32(np_tim, "sr_idle",
|
||||
&timing->sr_idle);
|
||||
ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
|
||||
&timing->sr_mc_gate_idle);
|
||||
ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
|
||||
&timing->srpd_lite_idle);
|
||||
ret |= of_property_read_u32(np_tim, "standby_idle",
|
||||
&timing->standby_idle);
|
||||
ret |= of_property_read_u32(np_tim, "auto_lp_dis_freq",
|
||||
&timing->auto_lp_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_dll_dis_freq",
|
||||
&timing->ddr3_dll_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
|
||||
&timing->phy_dll_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
|
||||
&timing->ddr3_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_drv",
|
||||
&timing->ddr3_drv);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_odt",
|
||||
&timing->ddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
|
||||
&timing->phy_ddr3_ca_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
|
||||
&timing->phy_ddr3_dq_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
|
||||
&timing->phy_ddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
|
||||
&timing->lpddr3_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr3_drv",
|
||||
&timing->lpddr3_drv);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr3_odt",
|
||||
&timing->lpddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
|
||||
&timing->phy_lpddr3_ca_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
|
||||
&timing->phy_lpddr3_dq_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
|
||||
&timing->phy_lpddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
|
||||
&timing->lpddr4_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_drv",
|
||||
&timing->lpddr4_drv);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
|
||||
&timing->lpddr4_dq_odt);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
|
||||
&timing->lpddr4_ca_odt);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
|
||||
&timing->phy_lpddr4_ca_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
|
||||
&timing->phy_lpddr4_ck_cs_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
|
||||
&timing->phy_lpddr4_dq_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
|
||||
&timing->phy_lpddr4_odt);
|
||||
if (ret) {
|
||||
devm_kfree(dev, timing);
|
||||
goto err;
|
||||
}
|
||||
of_node_put(np_tim);
|
||||
return timing;
|
||||
}
|
||||
|
||||
err:
|
||||
if (timing) {
|
||||
devm_kfree(dev, timing);
|
||||
timing = NULL;
|
||||
}
|
||||
of_node_put(np_tim);
|
||||
return timing;
|
||||
}
|
||||
|
||||
static int rk_drm_get_lcdc_type(void)
|
||||
{
|
||||
struct drm_device *drm;
|
||||
|
|
@ -892,6 +1427,51 @@ static int rk3288_dmc_init(struct platform_device *pdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int rk3328_dmc_init(struct platform_device *pdev,
|
||||
struct rockchip_dmcfreq *dmcfreq)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
u32 size;
|
||||
|
||||
res = sip_smc_dram(0, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
|
||||
dev_notice(&pdev->dev, "current ATF version 0x%lx!\n", res.a1);
|
||||
if (res.a0 || (res.a1 < 0x101)) {
|
||||
dev_err(&pdev->dev,
|
||||
"trusted firmware need to update or is invalid!\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
dev_notice(&pdev->dev, "read tf version 0x%lx!\n", res.a1);
|
||||
|
||||
/*
|
||||
* first 4KB is used for interface parameters
|
||||
* after 4KB * N is dts parameters
|
||||
*/
|
||||
size = sizeof(struct rk3328_ddr_dts_config_timing);
|
||||
res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
|
||||
SHARE_PAGE_TYPE_DDR);
|
||||
if (res.a0 != 0) {
|
||||
dev_err(&pdev->dev, "no ATF memory for init\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
ddr_psci_param = (struct share_params *)res.a1;
|
||||
of_get_rk3328_timings(&pdev->dev, pdev->dev.of_node,
|
||||
(uint32_t *)ddr_psci_param);
|
||||
|
||||
res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_INIT);
|
||||
if (res.a0) {
|
||||
dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
|
||||
res.a0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rk3368_dmc_init(struct platform_device *pdev,
|
||||
struct rockchip_dmcfreq *dmcfreq)
|
||||
{
|
||||
|
|
@ -972,94 +1552,6 @@ static int rk3368_dmc_init(struct platform_device *pdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct rk3399_dram_timing *of_get_rk3399_timings(struct device *dev,
|
||||
struct device_node *np)
|
||||
{
|
||||
struct rk3399_dram_timing *timing = NULL;
|
||||
struct device_node *np_tim;
|
||||
int ret;
|
||||
|
||||
np_tim = of_parse_phandle(np, "ddr_timing", 0);
|
||||
if (np_tim) {
|
||||
timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
|
||||
if (!timing)
|
||||
goto err;
|
||||
|
||||
ret = of_property_read_u32(np_tim, "ddr3_speed_bin",
|
||||
&timing->ddr3_speed_bin);
|
||||
ret |= of_property_read_u32(np_tim, "pd_idle",
|
||||
&timing->pd_idle);
|
||||
ret |= of_property_read_u32(np_tim, "sr_idle",
|
||||
&timing->sr_idle);
|
||||
ret |= of_property_read_u32(np_tim, "sr_mc_gate_idle",
|
||||
&timing->sr_mc_gate_idle);
|
||||
ret |= of_property_read_u32(np_tim, "srpd_lite_idle",
|
||||
&timing->srpd_lite_idle);
|
||||
ret |= of_property_read_u32(np_tim, "standby_idle",
|
||||
&timing->standby_idle);
|
||||
ret |= of_property_read_u32(np_tim, "auto_lp_dis_freq",
|
||||
&timing->auto_lp_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_dll_dis_freq",
|
||||
&timing->ddr3_dll_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "phy_dll_dis_freq",
|
||||
&timing->phy_dll_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_odt_dis_freq",
|
||||
&timing->ddr3_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_drv",
|
||||
&timing->ddr3_drv);
|
||||
ret |= of_property_read_u32(np_tim, "ddr3_odt",
|
||||
&timing->ddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "phy_ddr3_ca_drv",
|
||||
&timing->phy_ddr3_ca_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_ddr3_dq_drv",
|
||||
&timing->phy_ddr3_dq_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_ddr3_odt",
|
||||
&timing->phy_ddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr3_odt_dis_freq",
|
||||
&timing->lpddr3_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr3_drv",
|
||||
&timing->lpddr3_drv);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr3_odt",
|
||||
&timing->lpddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr3_ca_drv",
|
||||
&timing->phy_lpddr3_ca_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr3_dq_drv",
|
||||
&timing->phy_lpddr3_dq_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr3_odt",
|
||||
&timing->phy_lpddr3_odt);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_odt_dis_freq",
|
||||
&timing->lpddr4_odt_dis_freq);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_drv",
|
||||
&timing->lpddr4_drv);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_dq_odt",
|
||||
&timing->lpddr4_dq_odt);
|
||||
ret |= of_property_read_u32(np_tim, "lpddr4_ca_odt",
|
||||
&timing->lpddr4_ca_odt);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_ca_drv",
|
||||
&timing->phy_lpddr4_ca_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_ck_cs_drv",
|
||||
&timing->phy_lpddr4_ck_cs_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_dq_drv",
|
||||
&timing->phy_lpddr4_dq_drv);
|
||||
ret |= of_property_read_u32(np_tim, "phy_lpddr4_odt",
|
||||
&timing->phy_lpddr4_odt);
|
||||
if (ret) {
|
||||
devm_kfree(dev, timing);
|
||||
goto err;
|
||||
}
|
||||
of_node_put(np_tim);
|
||||
return timing;
|
||||
}
|
||||
|
||||
err:
|
||||
if (timing) {
|
||||
devm_kfree(dev, timing);
|
||||
timing = NULL;
|
||||
}
|
||||
of_node_put(np_tim);
|
||||
return timing;
|
||||
}
|
||||
|
||||
static int rk3399_dmc_init(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -1100,6 +1592,7 @@ static int rk3399_dmc_init(struct platform_device *pdev)
|
|||
static const struct of_device_id rockchip_dmcfreq_of_match[] = {
|
||||
{ .compatible = "rockchip,rk3128-dmc", .data = rk3128_dmc_init },
|
||||
{ .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
|
||||
{ .compatible = "rockchip,rk3328-dmc", .data = rk3328_dmc_init },
|
||||
{ .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
|
||||
{ .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
|
||||
{ },
|
||||
|
|
|
|||
|
|
@ -16,31 +16,45 @@
|
|||
#ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
#define _DT_BINDINGS_CLOCK_ROCKCHIP_DDR_H
|
||||
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
#define DDR3_800D (0) /* 5-5-5 */
|
||||
#define DDR3_800E (1) /* 6-6-6 */
|
||||
#define DDR3_1066E (2) /* 6-6-6 */
|
||||
#define DDR3_1066F (3) /* 7-7-7 */
|
||||
#define DDR3_1066G (4) /* 8-8-8 */
|
||||
#define DDR3_1333F (5) /* 7-7-7 */
|
||||
#define DDR3_1333G (6) /* 8-8-8 */
|
||||
#define DDR3_1333H (7) /* 9-9-9 */
|
||||
#define DDR3_1333J (8) /* 10-10-10 */
|
||||
#define DDR3_1600G (9) /* 8-8-8 */
|
||||
#define DDR3_1600H (10) /* 9-9-9 */
|
||||
#define DDR3_1600J (11) /* 10-10-10 */
|
||||
#define DDR3_1600K (12) /* 11-11-11 */
|
||||
#define DDR3_1866J (13) /* 10-10-10 */
|
||||
#define DDR3_1866K (14) /* 11-11-11 */
|
||||
#define DDR3_1866L (15) /* 12-12-12 */
|
||||
#define DDR3_1866M (16) /* 13-13-13 */
|
||||
#define DDR3_2133K (17) /* 11-11-11 */
|
||||
#define DDR3_2133L (18) /* 12-12-12 */
|
||||
#define DDR3_2133M (19) /* 13-13-13 */
|
||||
#define DDR3_2133N (20) /* 14-14-14 */
|
||||
#define DDR3_DEFAULT (21)
|
||||
#define DDR_DDR2 (22)
|
||||
#define DDR_LPDDR (23)
|
||||
#define DDR_LPDDR2 (24)
|
||||
|
||||
#define DDR4_1600J (0) /* 10-10-10 */
|
||||
#define DDR4_1600K (1) /* 11-11-11 */
|
||||
#define DDR4_1600L (2) /* 12-12-12 */
|
||||
#define DDR4_1866L (3) /* 12-12-12 */
|
||||
#define DDR4_1866M (4) /* 13-13-13 */
|
||||
#define DDR4_1866N (5) /* 14-14-14 */
|
||||
#define DDR4_2133N (6) /* 14-14-14 */
|
||||
#define DDR4_2133P (7) /* 15-15-15 */
|
||||
#define DDR4_2133R (8) /* 16-16-16 */
|
||||
#define DDR4_2400P (9) /* 15-15-15 */
|
||||
#define DDR4_2400R (10) /* 16-16-16 */
|
||||
#define DDR4_2400U (11) /* 18-18-18 */
|
||||
#define DDR4_DEFAULT (12)
|
||||
|
||||
#define PAUSE_CPU_STACK_SIZE 16
|
||||
|
||||
|
|
|
|||
159
include/dt-bindings/memory/rk3328-dram.h
Normal file
159
include/dt-bindings/memory/rk3328-dram.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/*
|
||||
* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This library is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H
|
||||
|
||||
#define DDR3_DS_34ohm (34)
|
||||
#define DDR3_DS_40ohm (40)
|
||||
|
||||
#define DDR3_ODT_DIS (0)
|
||||
#define DDR3_ODT_40ohm (40)
|
||||
#define DDR3_ODT_60ohm (60)
|
||||
#define DDR3_ODT_120ohm (120)
|
||||
|
||||
#define LP2_DS_34ohm (34)
|
||||
#define LP2_DS_40ohm (40)
|
||||
#define LP2_DS_48ohm (48)
|
||||
#define LP2_DS_60ohm (60)
|
||||
#define LP2_DS_68_6ohm (68) /* optional */
|
||||
#define LP2_DS_80ohm (80)
|
||||
#define LP2_DS_120ohm (120) /* optional */
|
||||
|
||||
#define LP3_DS_34ohm (34)
|
||||
#define LP3_DS_40ohm (40)
|
||||
#define LP3_DS_48ohm (48)
|
||||
#define LP3_DS_60ohm (60)
|
||||
#define LP3_DS_80ohm (80)
|
||||
#define LP3_DS_34D_40U (3440)
|
||||
#define LP3_DS_40D_48U (4048)
|
||||
#define LP3_DS_34D_48U (3448)
|
||||
|
||||
#define LP3_ODT_DIS (0)
|
||||
#define LP3_ODT_60ohm (60)
|
||||
#define LP3_ODT_120ohm (120)
|
||||
#define LP3_ODT_240ohm (240)
|
||||
|
||||
#define LP4_PDDS_40ohm (40)
|
||||
#define LP4_PDDS_48ohm (48)
|
||||
#define LP4_PDDS_60ohm (60)
|
||||
#define LP4_PDDS_80ohm (80)
|
||||
#define LP4_PDDS_120ohm (120)
|
||||
#define LP4_PDDS_240ohm (240)
|
||||
|
||||
#define LP4_DQ_ODT_40ohm (40)
|
||||
#define LP4_DQ_ODT_48ohm (48)
|
||||
#define LP4_DQ_ODT_60ohm (60)
|
||||
#define LP4_DQ_ODT_80ohm (80)
|
||||
#define LP4_DQ_ODT_120ohm (120)
|
||||
#define LP4_DQ_ODT_240ohm (240)
|
||||
#define LP4_DQ_ODT_DIS (0)
|
||||
|
||||
#define LP4_CA_ODT_40ohm (40)
|
||||
#define LP4_CA_ODT_48ohm (48)
|
||||
#define LP4_CA_ODT_60ohm (60)
|
||||
#define LP4_CA_ODT_80ohm (80)
|
||||
#define LP4_CA_ODT_120ohm (120)
|
||||
#define LP4_CA_ODT_240ohm (240)
|
||||
#define LP4_CA_ODT_DIS (0)
|
||||
|
||||
#define DDR4_DS_34ohm (34)
|
||||
#define DDR4_DS_48ohm (48)
|
||||
#define DDR4_RTT_NOM_DIS (0)
|
||||
#define DDR4_RTT_NOM_60ohm (60)
|
||||
#define DDR4_RTT_NOM_120ohm (120)
|
||||
#define DDR4_RTT_NOM_40ohm (40)
|
||||
#define DDR4_RTT_NOM_240ohm (240)
|
||||
#define DDR4_RTT_NOM_48ohm (48)
|
||||
#define DDR4_RTT_NOM_80ohm (80)
|
||||
#define DDR4_RTT_NOM_34ohm (34)
|
||||
|
||||
#define PHY_DDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR3_RON_RTT_451ohm (1)
|
||||
#define PHY_DDR3_RON_RTT_225ohm (2)
|
||||
#define PHY_DDR3_RON_RTT_150ohm (3)
|
||||
#define PHY_DDR3_RON_RTT_112ohm (4)
|
||||
#define PHY_DDR3_RON_RTT_90ohm (5)
|
||||
#define PHY_DDR3_RON_RTT_75ohm (6)
|
||||
#define PHY_DDR3_RON_RTT_64ohm (7)
|
||||
#define PHY_DDR3_RON_RTT_56ohm (16)
|
||||
#define PHY_DDR3_RON_RTT_50ohm (17)
|
||||
#define PHY_DDR3_RON_RTT_45ohm (18)
|
||||
#define PHY_DDR3_RON_RTT_41ohm (19)
|
||||
#define PHY_DDR3_RON_RTT_37ohm (20)
|
||||
#define PHY_DDR3_RON_RTT_34ohm (21)
|
||||
#define PHY_DDR3_RON_RTT_33ohm (22)
|
||||
#define PHY_DDR3_RON_RTT_30ohm (23)
|
||||
#define PHY_DDR3_RON_RTT_28ohm (24)
|
||||
#define PHY_DDR3_RON_RTT_26ohm (25)
|
||||
#define PHY_DDR3_RON_RTT_25ohm (26)
|
||||
#define PHY_DDR3_RON_RTT_23ohm (27)
|
||||
#define PHY_DDR3_RON_RTT_22ohm (28)
|
||||
#define PHY_DDR3_RON_RTT_21ohm (29)
|
||||
#define PHY_DDR3_RON_RTT_20ohm (30)
|
||||
#define PHY_DDR3_RON_RTT_19ohm (31)
|
||||
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_DISABLE (0)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_480ohm (1)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_240ohm (2)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_160ohm (3)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_120ohm (4)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_96ohm (5)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_80ohm (6)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_68ohm (7)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_60ohm (16)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_53ohm (17)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_48ohm (18)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_43ohm (19)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_40ohm (20)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_37ohm (21)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_34ohm (22)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_32ohm (23)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_30ohm (24)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_28ohm (25)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_26ohm (26)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_25ohm (27)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_24ohm (28)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_22ohm (29)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_21ohm (30)
|
||||
#define PHY_DDR4_LPDDR3_RON_RTT_20ohm (31)
|
||||
|
||||
#endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3328_H*/
|
||||
|
|
@ -23,5 +23,6 @@
|
|||
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user