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Merge branch 'lpc32xx/core' of git://git.antcom.de/linux-2.6 into next/soc

Browse Source 
A second batch of core patches for lpc32xx, based on top of the first
one in the lpc32xx-next branch.

* 'lpc32xx/core' of git://git.antcom.de/linux-2.6:
  ARM: LPC32xx: Remove unused gpios
  ARM: LPC32xx: Remove USB and I2C init from phy3250.c
  ARM: LPC32xx: Cleanup USB clock init
  ARM: LPC32xx: Remove wrong re-initialization of MMC clock register
  ARM: LPC32xx: Add further bits to MMC init
  ARM: LPC32xx: Init MMC via clock

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2012-07-03 21:45:50 +02:00
commit 47d4ed78d3
3 changed files with 92 additions and 30 deletions
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88
arch/arm/mach-lpc32xx/clock.c
View File

@ -739,14 +739,77 @@ static struct clk clk_rtc = {
.get_rate = local_return_parent_rate,
};
static int local_usb_enable(struct clk *clk, int enable)
{
u32 tmp;
if (enable) {
/* Set up I2C pull levels */
tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE;
__raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
}
return local_onoff_enable(clk, enable);
}
static struct clk clk_usbd = {
.parent = &clk_usbpll,
.enable = local_onoff_enable,
.enable = local_usb_enable,
.enable_reg = LPC32XX_CLKPWR_USB_CTRL,
.enable_mask = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
.get_rate = local_return_parent_rate,
};
#define OTG_ALWAYS_MASK (LPC32XX_USB_OTG_OTG_CLOCK_ON | \
LPC32XX_USB_OTG_I2C_CLOCK_ON)
static int local_usb_otg_enable(struct clk *clk, int enable)
{
int to = 1000;
if (enable) {
__raw_writel(clk->enable_mask, clk->enable_reg);
while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
clk->enable_mask) != clk->enable_mask) && (to > 0))
to--;
} else {
__raw_writel(OTG_ALWAYS_MASK, clk->enable_reg);
while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0))
to--;
}
if (to)
return 0;
else
return -1;
}
static struct clk clk_usb_otg_dev = {
.parent = &clk_usbpll,
.enable = local_usb_otg_enable,
.enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
.enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
LPC32XX_USB_OTG_OTG_CLOCK_ON |
LPC32XX_USB_OTG_DEV_CLOCK_ON |
LPC32XX_USB_OTG_I2C_CLOCK_ON,
.get_rate = local_return_parent_rate,
};
static struct clk clk_usb_otg_host = {
.parent = &clk_usbpll,
.enable = local_usb_otg_enable,
.enable_reg = LPC32XX_USB_OTG_CLK_CTRL,
.enable_mask = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
LPC32XX_USB_OTG_OTG_CLOCK_ON |
LPC32XX_USB_OTG_HOST_CLOCK_ON |
LPC32XX_USB_OTG_I2C_CLOCK_ON,
.get_rate = local_return_parent_rate,
};
static int tsc_onoff_enable(struct clk *clk, int enable)
{
u32 tmp;
@ -812,11 +875,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable)
u32 tmp;
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS |
LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS |
LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS |
LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS);
/* If rate is 0, disable clock */
if (enable != 0)
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
@ -865,7 +934,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
static int mmc_set_rate(struct clk *clk, unsigned long rate)
{
u32 oldclk, tmp;
u32 tmp;
unsigned long prate, div, crate = mmc_round_rate(clk, rate);
prate = clk->parent->get_rate(clk->parent);
@ -873,16 +942,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate)
div = prate / crate;
/* The MMC clock must be on when accessing an MMC register */
oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
__raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
LPC32XX_CLKPWR_MS_CTRL);
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
__raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
return 0;
}
@ -1143,6 +1208,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd),
CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev),
CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host),
CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
};

14
arch/arm/mach-lpc32xx/include/mach/platform.h
View File

@ -694,4 +694,18 @@
#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
/*
* USB Otg Registers
*/
#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x))
#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4)
#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8)
/* USB OTG CLK CTRL bit defines */
#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4)
#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3)
#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2)
#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
#endif

20
arch/arm/mach-lpc32xx/phy3250.c
View File

@ -51,12 +51,9 @@
/*
* Mapped GPIOLIB GPIOs
*/
#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
/*
* AMBA LCD controller
@ -248,25 +245,8 @@ static void __init lpc3250_machine_init(void)
tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
__raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
/* Set up USB power */
tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
/* Set up I2C pull levels */
tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
__raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
lpc32xx_serial_init();
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
/* Test clock needed for UDA1380 initial init */
__raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,