From 8f0cc929a4bad534c5a860a53d88912cf16d9c9c Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 1 Apr 2026 11:29:41 +0100 Subject: [PATCH 1/9] arm64: tegra: Fix Tegra234 MGBE PTP clock The Tegra MGBE PTP clock is incorrectly named as 'ptp-ref' and not 'ptp_ref' and this causing the initialisation of the PTP clock to fail. The device-tree binding doc for the device and the Tegra MGBE driver have been updated to use the correct name and so update the device-tree for Tegra234 as well. Fixes: 610cdf3186bc ("arm64: tegra: Add MGBE nodes on Tegra234") Signed-off-by: Jon Hunter Reviewed-by: Krzysztof Kozlowski Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 04a95b6658ca..18220cdac9f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -3605,7 +3605,7 @@ ethernet@6800000 { <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>, @@ -3647,7 +3647,7 @@ ethernet@6900000 { <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>, @@ -3689,7 +3689,7 @@ ethernet@6a00000 { <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>, @@ -3731,7 +3731,7 @@ ethernet@6b00000 { <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>, <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>, <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>; - clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m", + clock-names = "mgbe", "mac", "mac-divider", "ptp_ref", "rx-input-m", "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m", "rx-pcs", "tx-pcs"; resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>, From d60ed99f1c9e0bdf1fcd713426f6213abe592c83 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Wed, 25 Mar 2026 00:39:59 +0530 Subject: [PATCH 2/9] arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes Add the aspm-l1-entry-delay-ns device tree property to all PCIe Root Port and PCIe Endpoint nodes in tegra194.dtsi and tegra234.dtsi so that ASPM L1 entrance latency is configured from device tree. - Tegra194: 4000 ns (4 us) for both Root Port and Endpoint. - Tegra234: 8000 ns (8 us) for Root Port, 16000 ns (16 us) for Endpoint. Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 9 +++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 16 ++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 849694f751d9..1d659454a6f9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2382,6 +2382,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2434,6 +2435,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2486,6 +2488,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2538,6 +2541,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2583,6 +2587,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; @@ -2629,6 +2634,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2674,6 +2680,7 @@ pcie-ep@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; @@ -2723,6 +2730,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; bus-range = <0x0 0xff>; @@ -2771,6 +2779,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <4000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 18220cdac9f9..75bb9a0ad027 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4532,6 +4532,7 @@ pcie@140a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4586,6 +4587,7 @@ pcie@140c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4640,6 +4642,7 @@ pcie@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4686,6 +4689,7 @@ pcie-ep@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; @@ -4734,6 +4738,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4788,6 +4793,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4842,6 +4848,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4896,6 +4903,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -4937,6 +4945,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; @@ -4983,6 +4992,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5037,6 +5047,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5083,6 +5094,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; @@ -5131,6 +5143,7 @@ pcie@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5177,6 +5190,7 @@ pcie-ep@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; @@ -5225,6 +5239,7 @@ pcie@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -5271,6 +5286,7 @@ pcie-ep@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; + aspm-l1-entry-delay-ns = <16000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; From 7f2eeae12690aaee6195f85ed129a29c17f156d1 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 19 May 2026 09:47:06 +0100 Subject: [PATCH 3/9] arm64: tegra: Fix address of Tegra264 main GPIO controller The 64-bit address of the main GPIO controller on Tegra264 is 0x810c300000. The main GPIO controller was incorrectly added under the bus@0 node instead of the bus@8100000000 node breaking the boot on Tegra264. Fix this by moving to main GPIO controller node under bus@8100000000. Fixes: c70e6bc11d20 ("arm64: tegra: Add Tegra264 GPIO controllers") Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra264.dtsi | 88 ++++++++++++------------ 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 06d8357bdf52..2d8e7e37830f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -3277,50 +3277,6 @@ rtc: rtc@c2c0000 { status = "disabled"; }; - gpio_main: gpio@c300000 { - compatible = "nvidia,tegra264-gpio"; - reg = <0x00 0x0c300000 0x0 0x4000>, - <0x00 0x0c310000 0x0 0x4000>; - reg-names = "security", "gpio"; - wakeup-parent = <&pmc>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - serial@c4e0000 { compatible = "nvidia,tegra264-utc"; reg = <0x0 0x0c4e0000 0x0 0x8000>, @@ -3586,6 +3542,50 @@ pci@c000000 { status = "disabled"; }; + gpio_main: gpio@c300000 { + compatible = "nvidia,tegra264-gpio"; + reg = <0x00 0x0c300000 0x0 0x4000>, + <0x00 0x0c310000 0x0 0x4000>; + reg-names = "security", "gpio"; + wakeup-parent = <&pmc>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + i2c14: i2c@c410000 { compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c410000 0x0 0x10000>; From 36532a9a22589a375556e16b103ae8275a4affc0 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 19 May 2026 09:47:07 +0100 Subject: [PATCH 4/9] arm64: tegra: Enable PCIe for Jetson AGX Thor Enable the PCIe controllers on the Jetson AGX Thor Developer Kit that are used for ethernet and NVMe. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../dts/nvidia/tegra264-p4071-0000+p3834-0008.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts index df6555b6d0e0..3bd4c4cf2871 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts +++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834-0008.dts @@ -8,4 +8,16 @@ / { model = "NVIDIA Jetson AGX Thor Developer Kit"; compatible = "nvidia,p4071-0000+p3834-0008", "nvidia,p3834-0008", "nvidia,tegra264"; + + bus@a800000000 { + /* PCIe C2 to enable Ethernet */ + pci@8420000 { + status = "okay"; + }; + + /* PCIe C5 to enable NVME */ + pci@8480000 { + status = "okay"; + }; + }; }; From 00b5b4e5d3c235950a80a7c5ca9297233640cbe9 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Thu, 14 May 2026 16:47:22 +0200 Subject: [PATCH 5/9] arm64: tegra: Mark MAX77620 as system power controller on Smaug Register the MAX77620 PMIC as the system power controller on Pixel C so the driver can install its sys-off handler. This allows the PMIC poweroff sequence to override the non-working PSCI SYSTEM_OFF implementation on this platform. Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index f0b8c2c80aa5..1791b47f0a73 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -1467,6 +1467,8 @@ pmic: pmic@3c { gpio-controller; #gpio-cells = <2>; + system-power-controller; + pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; From bba8eefb56480c7b06a25e99632b1b6510a25473 Mon Sep 17 00:00:00 2001 From: Manikanta Maddireddy Date: Fri, 15 May 2026 12:37:53 +0530 Subject: [PATCH 6/9] arm64: tegra: Fix aspm-l1-entry-delay-ns L1 latency cells The Tegra194 PCIe driver converts aspm-l1-entry-delay-ns to whole ms with ceiling division, then derives the Synopsys DesignWare PORT_AFR L1 entrance latency encoding as min(order_base_2(us), 7). The nanosecond values from the Fixes tag below round up to 4, 8, and 16 us, selecting PORT_AFR L1 entrance latency codes 2, 3, and 4 respectively. Raise the programmed latency so the PORT_AFR codes are 3 / 4 / 5 (8 / 16 / 32 us buckets) instead of 2 / 3 / 4 (4 / 8 / 16 us). - tegra194.dtsi: 4000 -> 8000 ns (all listed controllers) - tegra234.dtsi: 8000 -> 16000 ns (Root Port), 16000 -> 32000 ns (Endpoint) Fixes: d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes") Signed-off-by: Manikanta Maddireddy Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++------- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 ++++++++++++------------ 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1d659454a6f9..7bbf0e892724 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -2382,7 +2382,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2435,7 +2435,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2488,7 +2488,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2541,7 +2541,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2587,7 +2587,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>; @@ -2634,7 +2634,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2680,7 +2680,7 @@ pcie-ep@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>; @@ -2730,7 +2730,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; bus-range = <0x0 0xff>; @@ -2779,7 +2779,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <4000>; + aspm-l1-entry-delay-ns = <8000>; interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 75bb9a0ad027..8e0c51e496e2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -4532,7 +4532,7 @@ pcie@140a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4587,7 +4587,7 @@ pcie@140c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4642,7 +4642,7 @@ pcie@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4689,7 +4689,7 @@ pcie-ep@140e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>; @@ -4738,7 +4738,7 @@ pcie@14100000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4793,7 +4793,7 @@ pcie@14120000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4848,7 +4848,7 @@ pcie@14140000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4903,7 +4903,7 @@ pcie@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -4945,7 +4945,7 @@ pcie-ep@14160000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>; @@ -4992,7 +4992,7 @@ pcie@14180000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5047,7 +5047,7 @@ pcie@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5094,7 +5094,7 @@ pcie-ep@141a0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>; @@ -5143,7 +5143,7 @@ pcie@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5190,7 +5190,7 @@ pcie-ep@141c0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>; @@ -5239,7 +5239,7 @@ pcie@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <8000>; + aspm-l1-entry-delay-ns = <16000>; bus-range = <0x0 0xff>; @@ -5286,7 +5286,7 @@ pcie-ep@141e0000 { nvidia,aspm-cmrt-us = <60>; nvidia,aspm-pwr-on-t-us = <20>; nvidia,aspm-l0s-entrance-latency-us = <3>; - aspm-l1-entry-delay-ns = <16000>; + aspm-l1-entry-delay-ns = <32000>; interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>, <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>; From f0fbedccae9e16624977cca02216ab2399f5a3ab Mon Sep 17 00:00:00 2001 From: Brian Norris Date: Tue, 28 Apr 2026 13:06:58 -0700 Subject: [PATCH 7/9] arm64: tegra: Add #{address,size}-cells to Chromium-based /firmware Chromium/Depthcharge bootloaders may dynamically add a few device nodes to a system's DTB under a /firmware node. A typical DT looks something like the following: / { firmware { ranges; coreboot { compatible = "coreboot"; reg = <...>; ...; }; }; }; Notably, the /firmware node has an empty 'ranges', but does not have address/size-cells. Commit 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") started requiring #address-cells for a device's parent if we want to use the reg resource in a device node. This leads to errors like the following: [ 7.763870] coreboot_table firmware:coreboot: probe with driver coreboot_table failed with error -22 Add appropriate #{address,size}-cells to work around the problem. Note that Google has also patched the Depthcharge bootloader source to add {address,size}-cells [1], but bootloader updates are typically delivered only via Google OS updates. Not all users install Google software updates, and even if they do, Google may not produce updated binaries for all/older devices. [1] https://lore.kernel.org/all/20241209092809.GA3246424@google.com/ https://crrev.com/c/6051580 ("coreboot: Insert #address-cells and #size-cells for firmware node") Closes: https://lore.kernel.org/all/aeKlYzTiL0OB1y3g@google.com/ Fixes: 6e5773d52f4a ("of/address: Fix WARN when attempting translating non-translatable addresses") Signed-off-by: Brian Norris Reviewed-by: Douglas Anderson Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132-norrin.dts | 5 +++++ arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts index 683ac124523b..1f5222d43e62 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts +++ b/arch/arm64/boot/dts/nvidia/tegra132-norrin.dts @@ -18,6 +18,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts index 1791b47f0a73..e0fde65a552b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-smaug.dts @@ -25,6 +25,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + firmware { + #address-cells = <2>; + #size-cells = <2>; + }; + memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0xc0000000>; From 3b7b80753c1f1a2e0d5f901d3ea1b75f258bb9de Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sat, 1 Nov 2025 18:01:10 -0500 Subject: [PATCH 8/9] Revert "arm64: tegra: Disable ISO SMMU for Tegra194" This reverts commit ebea268ea583ba4970df425dfef8c8e21d0a4e12. Mmu is now being enabled for the display controllers. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 7bbf0e892724..5042224d8736 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1795,7 +1795,7 @@ iommu@10000000 { #iommu-cells = <1>; nvidia,memory-controller = <&mc>; - status = "disabled"; + status = "okay"; }; smmu: iommu@12000000 { From e1215cd6d3b9338e72573cc1cc60922b5bd34da4 Mon Sep 17 00:00:00 2001 From: Aaron Kling Date: Sat, 1 Nov 2025 18:01:11 -0500 Subject: [PATCH 9/9] arm64: tegra: Enable SMMU on Tegra194 display controllers These use a separate SMMU instance compared to everything else currently enabled for the SoC. Signed-off-by: Aaron Kling Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5042224d8736..eb7e3c666df6 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1722,7 +1722,7 @@ bpmp-noc@d600000 { nvidia,apbmisc = <&apbmisc>; }; - iommu@10000000 { + smmu_iso: iommu@10000000 { compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500"; reg = <0x0 0x10000000 0x0 0x800000>; interrupts = , @@ -1962,6 +1962,7 @@ display@15200000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <0>; @@ -1980,6 +1981,7 @@ display@15210000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <1>; @@ -1998,6 +2000,7 @@ display@15220000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <2>; @@ -2016,6 +2019,7 @@ display@15230000 { interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>, <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>; interconnect-names = "dma-mem", "read-1"; + iommus = <&smmu_iso TEGRA194_SID_NVDISPLAY>; nvidia,outputs = <&sor0 &sor1 &sor2 &sor3>; nvidia,head = <3>;