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mtd: rawnand: qcom: Fix last codeword read in qcom_param_page_type_exec()
For QPIC V2 onwards there is a separate register to read
last code word "QPIC_NAND_READ_LOCATION_LAST_CW_n".
qcom_param_page_type_exec() is used to read only one code word
If it configures the number of code words to 1 in QPIC_NAND_DEV0_CFG0
register then QPIC controller thinks its reading the last code word,
since we are having separate register to read the last code word,
we have to configure "QPIC_NAND_READ_LOCATION_LAST_CW_n" register
to fetch data from QPIC buffer to system memory.
Without this change page read was failing with timeout error
/ # hexdump -C /dev/mtd1
[ 129.206113] qcom-nandc 1cc8000.nand-controller: failure to read page/oob
hexdump: /dev/mtd1: Connection timed out
This issue only seen on SDX targets since SDX target used QPICv2. But
same working on IPQ targets since IPQ used QPICv1.
Cc: stable@vger.kernel.org
Fixes: 89550beb09 ("mtd: rawnand: qcom: Implement exec_op()")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Lakshmi Sowjanya D <quic_laksd@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
This commit is contained in:
parent
ee000969f2
commit
47bddabbf6
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@ -1863,7 +1863,12 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_
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const struct nand_op_instr *instr = NULL;
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unsigned int op_id = 0;
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unsigned int len = 0;
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int ret;
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int ret, reg_base;
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reg_base = NAND_READ_LOCATION_0;
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if (nandc->props->qpic_version2)
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reg_base = NAND_READ_LOCATION_LAST_CW_0;
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ret = qcom_parse_instructions(chip, subop, &q_op);
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if (ret)
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@ -1915,7 +1920,10 @@ static int qcom_param_page_type_exec(struct nand_chip *chip, const struct nand_
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op_id = q_op.data_instr_idx;
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len = nand_subop_get_data_len(subop, op_id);
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nandc_set_read_loc(chip, 0, 0, 0, len, 1);
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if (nandc->props->qpic_version2)
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nandc_set_read_loc_last(chip, reg_base, 0, len, 1);
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else
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nandc_set_read_loc_first(chip, reg_base, 0, len, 1);
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if (!nandc->props->qpic_version2) {
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qcom_write_reg_dma(nandc, &nandc->regs->vld, NAND_DEV_CMD_VLD, 1, 0);
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