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arm64: dts: rockchip: Add overlay for the PCIe slot on RK3576 EVB1
Rockchip RK3576 EVB1 has an onboard PCIe slot (PCIe 2.1, x4 mechanically, x1 electrically), but it shares pins and PHY with the only USB3 Type-A port. There is a physical switch next to the slot to transfer respective pins connection from the USB3 port to the PCIe slot, but apart from flipping the switch one must also disable the USB3 host controller to prevent it from claiming the PHY before the PCIe slot can become usable. Add an overlay to disable the USB3 host port and instead enable the PCIe slot, along with its pin configs. The physical switch must still be flipped to the "ON - PCIe1" position for this to work. Signed-off-by: Alexey Charkov <alchark@gmail.com> Link: https://patch.msgid.link/20251202-evb1-pcie1-v2-1-810693b1b72f@gmail.com Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-100ask-dshanpi-a1.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-luckfox-omni3576.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-m5.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-nanopi-r76s.dtb
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@ -259,6 +260,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-armsom-sige5-v1.2-wifibt.dtb
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rk3576-armsom-sige5-v1.2-wifibt-dtbs := rk3576-armsom-sige5.dtb \
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rk3576-armsom-sige5-v1.2-wifibt.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3576-evb1-v10-pcie1.dtb
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rk3576-evb1-v10-pcie1-dtbs := rk3576-evb1-v10.dtb \
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rk3576-evb1-v10-pcie1.dtbo
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dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-wifi.dtb
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rk3588-edgeble-neu6a-wifi-dtbs := rk3588-edgeble-neu6a-io.dtb \
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rk3588-edgeble-neu6a-wifi.dtbo
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31
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso
Normal file
31
arch/arm64/boot/dts/rockchip/rk3576-evb1-v10-pcie1.dtso
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* DT-overlay to enable the onboard PCIe x1 slot, which shares pins and the PHY
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* with the USB3 host port.
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* To use the PCIe slot, apply this overlay and flip the Dial_Switch_1 right
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* next to the PCIe slot to low state (labeled "ON - PCIe1"). USB3 host port
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* will be unusable (not even in 2.0 mode)
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/pinctrl/rockchip.h>
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&pcie1 {
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pinctrl-0 = <&pcie1m0_pins &pcie1_rst>;
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pinctrl-names = "default";
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status = "okay";
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};
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&pinctrl {
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pcie1 {
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pcie1_rst: pcie1-rst {
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rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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};
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&usb_drd1_dwc3 {
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status = "disabled";
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};
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