From 4717a648249726c8f4ee6332de6206f0ae5f20de Mon Sep 17 00:00:00 2001
From: Amir Vajid <avajid@codeaurora.org>
Date: Thu, 26 Aug 2021 14:54:07 -0700
Subject: [PATCH] sched: walt: add sched_switch_ctrs_cfg event

Create an event to periodically dump the configuration
of the pmu counter registers. This can be used in
conjunction with the existing sched_switch_with_ctrs
event to confirm which counter is configured in each
register.

Change-Id: Iaf11279e94d4af3f8aff522282585e680acd5f4d
Signed-off-by: Amir Vajid <avajid@codeaurora.org>
---
 kernel/sched/walt/perf_trace_counters.h | 52 +++++++++++++++++++++++++
 kernel/sched/walt/walt_tp.c             |  7 ++++
 2 files changed, 59 insertions(+)

diff --git a/kernel/sched/walt/perf_trace_counters.h b/kernel/sched/walt/perf_trace_counters.h
index 62f86b08a487..bcf318c2ebb1 100644
--- a/kernel/sched/walt/perf_trace_counters.h
+++ b/kernel/sched/walt/perf_trace_counters.h
@@ -18,6 +18,7 @@
 #define C4 0x10
 #define C5 0x20
 #define C_ALL (CC | C0 | C1 | C2 | C3 | C4 | C5)
+#define TYPE_MASK 0xFFFF
 #define NUM_L1_CTRS 6
 #define NUM_AMU_CTRS 2
 
@@ -117,6 +118,57 @@ TRACE_EVENT(sched_switch_with_ctrs,
 				__entry->amu0, __entry->amu1)
 );
 
+TRACE_EVENT(sched_switch_ctrs_cfg,
+
+		TP_PROTO(int cpu),
+
+		TP_ARGS(cpu),
+
+		TP_STRUCT__entry(
+			__field(int, cpu)
+			__field(unsigned long, ctr0)
+			__field(unsigned long, ctr1)
+			__field(unsigned long, ctr2)
+			__field(unsigned long, ctr3)
+			__field(unsigned long, ctr4)
+			__field(unsigned long, ctr5)
+		),
+
+		TP_fast_assign(
+			u32 i;
+			u32 cnten_val;
+			u32 ctr_type[NUM_L1_CTRS] = {0};
+
+			cnten_val = per_cpu(cntenset_val, cpu);
+
+			for (i = 0; i < NUM_L1_CTRS; i++) {
+				if (cnten_val & (1 << i)) {
+					/* Select */
+					write_sysreg(i, pmselr_el0);
+					isb();
+					/* Read type */
+					ctr_type[i] = read_sysreg(pmxevtyper_el0)
+								& TYPE_MASK;
+				} else
+					ctr_type[i] = 0;
+			}
+
+			__entry->cpu  = cpu;
+			__entry->ctr0 = ctr_type[0];
+			__entry->ctr1 = ctr_type[1];
+			__entry->ctr2 = ctr_type[2];
+			__entry->ctr3 = ctr_type[3];
+			__entry->ctr4 = ctr_type[4];
+			__entry->ctr5 = ctr_type[5];
+		),
+
+		TP_printk("cpu=%d CTR0=%lu CTR1=%lu CTR2=%lu CTR3=%lu CTR4=%lu CTR5=%lu",
+				__entry->cpu,
+				__entry->ctr0, __entry->ctr1,
+				__entry->ctr2, __entry->ctr3,
+				__entry->ctr4, __entry->ctr5)
+);
+
 #endif
 #undef TRACE_INCLUDE_PATH
 #define TRACE_INCLUDE_PATH ../../kernel/sched/walt
diff --git a/kernel/sched/walt/walt_tp.c b/kernel/sched/walt/walt_tp.c
index 3c98161e889f..62d3acb2b482 100644
--- a/kernel/sched/walt/walt_tp.c
+++ b/kernel/sched/walt/walt_tp.c
@@ -20,6 +20,7 @@ DEFINE_PER_CPU(unsigned long[NUM_L1_CTRS], previous_l1_cnts);
 DEFINE_PER_CPU(unsigned long[NUM_AMU_CTRS], previous_amu_cnts);
 DEFINE_PER_CPU(u32, old_pid);
 DEFINE_PER_CPU(u32, hotplug_flag);
+DEFINE_PER_CPU(u64, prev_time);
 
 static int tracectr_cpu_hotplug_coming_up(unsigned int cpu)
 {
@@ -54,6 +55,7 @@ void tracectr_notifier(void *ignore, bool preempt,
 	u32 cnten_val;
 	int current_pid;
 	u32 cpu = task_cpu(next);
+	u64 now;
 
 	if (!trace_sched_switch_with_ctrs_enabled())
 		return;
@@ -71,6 +73,11 @@ void tracectr_notifier(void *ignore, bool preempt,
 		} else {
 			trace_sched_switch_with_ctrs(per_cpu(old_pid, cpu),
 						     current_pid);
+			now = sched_clock();
+			if ((now - per_cpu(prev_time, cpu)) > NSEC_PER_SEC) {
+				trace_sched_switch_ctrs_cfg(cpu);
+				per_cpu(prev_time, cpu) = now;
+			}
 		}
 
 		/* Enable all the counters that were disabled */