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net: phy: realtek: demystify PHYSR register location

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Turns out that register address RTL_VND2_PHYSR (0xa434) maps to
Clause-22 register MII_RESV2. Use that to get rid of yet another magic
number, and rename access macros accordingly.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Link: https://patch.msgid.link/6ed246e0aa3ca8038d2fa432d51518959fb89b6b.1768275364.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Daniel Golle 2026-01-13 03:44:33 +00:00 committed by Jakub Kicinski
parent 85f75da86a
commit 46ff862d37
1 changed files with 13 additions and 13 deletions
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26
drivers/net/phy/realtek/realtek_main.c
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@ -179,12 +179,12 @@
#define RTL9000A_GINMR 0x14
#define RTL9000A_GINMR_LINK_STATUS BIT(4)
#define RTL_VND2_PHYSR 0xa434
#define RTL_VND2_PHYSR_DUPLEX BIT(3)
#define RTL_VND2_PHYSR_SPEEDL GENMASK(5, 4)
#define RTL_VND2_PHYSR_SPEEDH GENMASK(10, 9)
#define RTL_VND2_PHYSR_MASTER BIT(11)
#define RTL_VND2_PHYSR_SPEED_MASK (RTL_VND2_PHYSR_SPEEDL | RTL_VND2_PHYSR_SPEEDH)
#define RTL_PHYSR MII_RESV2
#define RTL_PHYSR_DUPLEX BIT(3)
#define RTL_PHYSR_SPEEDL GENMASK(5, 4)
#define RTL_PHYSR_SPEEDH GENMASK(10, 9)
#define RTL_PHYSR_MASTER BIT(11)
#define RTL_PHYSR_SPEED_MASK (RTL_PHYSR_SPEEDL | RTL_PHYSR_SPEEDH)
#define RTL_MDIO_PCS_EEE_ABLE 0xa5c4
#define RTL_MDIO_AN_EEE_ADV 0xa5d0
@ -1103,12 +1103,12 @@ static void rtlgen_decode_physr(struct phy_device *phydev, int val)
* 0: Half Duplex
* 1: Full Duplex
*/
if (val & RTL_VND2_PHYSR_DUPLEX)
if (val & RTL_PHYSR_DUPLEX)
phydev->duplex = DUPLEX_FULL;
else
phydev->duplex = DUPLEX_HALF;
switch (val & RTL_VND2_PHYSR_SPEED_MASK) {
switch (val & RTL_PHYSR_SPEED_MASK) {
case 0x0000:
phydev->speed = SPEED_10;
break;
@ -1136,7 +1136,7 @@ static void rtlgen_decode_physr(struct phy_device *phydev, int val)
* 1: Master Mode
*/
if (phydev->speed >= 1000) {
if (val & RTL_VND2_PHYSR_MASTER)
if (val & RTL_PHYSR_MASTER)
phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER;
else
phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE;
@ -1156,8 +1156,7 @@ static int rtlgen_read_status(struct phy_device *phydev)
if (!phydev->link)
return 0;
val = phy_read_paged(phydev, RTL822X_VND2_TO_PAGE(RTL_VND2_PHYSR),
RTL822X_VND2_TO_PAGE_REG(RTL_VND2_PHYSR));
val = phy_read(phydev, RTL_PHYSR);
if (val < 0)
return val;
@ -1624,7 +1623,8 @@ static int rtl822x_c45_read_status(struct phy_device *phydev)
}
/* Read actual speed from vendor register. */
val = phy_read_mmd(phydev, MDIO_MMD_VEND2, RTL_VND2_PHYSR);
val = phy_read_mmd(phydev, MDIO_MMD_VEND2,
RTL822X_VND2_C22_REG(RTL_PHYSR));
if (val < 0)
return val;
@ -2128,7 +2128,7 @@ static int rtlgen_sfp_read_status(struct phy_device *phydev)
if (!phydev->link)
return 0;
val = rtlgen_read_vend2(phydev, RTL_VND2_PHYSR);
val = phy_read(phydev, RTL_PHYSR);
if (val < 0)
return val;