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arm64: dts: qcom: glymur: Fix cache and SRAM simple_bus_reg warnings

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Correct the unit address of cache controller and SRAM nodes in Qualcomm
Glymur SoC DTSI to fix W=1 DTC warnings:

  glymur.dtsi:5876.36-5908.5: Warning (simple_bus_reg): /soc@0/system-cache-controller@20400000: simple-bus unit address format error, expected "21800000"
  glymur.dtsi:5917.23-5934.5: Warning (simple_bus_reg): /soc@0/sram@81e08000: simple-bus unit address format error, expected "81e08600"

Fixes: 41b6e8db40 ("arm64: dts: qcom: Introduce Glymur base dtsi")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260405-dts-qcom-w-1-fixes-v2-2-1f2c7b74a93f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2026-04-05 15:39:29 +02:00 committed by Bjorn Andersson
parent cd66b6d256
commit 46eccc1034
1 changed files with 2 additions and 2 deletions
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arch/arm64/boot/dts/qcom/glymur.dtsi
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@ -5873,7 +5873,7 @@ oobm_ss_noc: interconnect@1f300000 {
#interconnect-cells = <2>;
};
system-cache-controller@20400000 {
system-cache-controller@21800000 {
compatible = "qcom,glymur-llcc";
reg = <0x0 0x21800000 0x0 0x100000>,
<0x0 0x21a00000 0x0 0x100000>,
@ -5914,7 +5914,7 @@ nsp_noc: interconnect@320c0000 {
#interconnect-cells = <2>;
};
imem: sram@81e08000 {
imem: sram@81e08600 {
compatible = "mmio-sram";
reg = <0x0 0x81e08600 0x0 0x300>;