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clk: tegra: support 48MHz clock for pll_p_out1

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UEFI on Surface2 sets pll_p_out1 to 48MHz which is not supported by kernel
and causes BUG() early on. Add 48MHz clock support for pll_p_out1.

Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
This commit is contained in:
Dmitry Osipenko 2026-06-25 11:30:52 +03:00 committed by Brian Masney
parent 5ffa9d308c
commit 46e31d69a5
1 changed files with 1 additions and 0 deletions
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1
drivers/clk/tegra/clk-pll.c
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@ -575,6 +575,7 @@ static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
break;
case 9600000:
case 28800000:
case 48000000:
/*
* PLL_P_OUT1 rate is not listed in PLLA table
*/