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x86/mce: Add enumeration for Intel bitfix filter reset

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IA32_CORE_CAPABILITIES enumerates the bitfix filter reset feature.

Intel specifies two values for the threshold status field in the
IA32_MCi_STATUS MSR:
	1 = GREEN (threshold has not been reached)
	2 = YELLOW (threshold exceeded, try bitfix filter reset)

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://patch.msgid.link/20260828153002.10290-3-tony.luck@intel.com
This commit is contained in:
Tony Luck 2026-08-28 08:29:57 -07:00
parent 179b100b45
commit 46cff0be63
2 changed files with 7 additions and 0 deletions
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5
arch/x86/include/asm/mce.h
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@ -13,6 +13,7 @@
#define MCG_CTL_P BIT_ULL(8) /* MCG_CTL register available */
#define MCG_EXT_P BIT_ULL(9) /* Extended registers available */
#define MCG_CMCI_P BIT_ULL(10) /* CMCI supported */
#define MCG_TES_P BIT_ULL(11) /* Threshold-based error status supported */
#define MCG_SEAM_NR BIT_ULL(12) /* MCG_STATUS_SEAM_NR supported */
#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
#define MCG_EXT_CNT_SHIFT 16
@ -41,6 +42,10 @@
#define MCI_STATUS_PCC BIT_ULL(57) /* processor context corrupt */
#define MCI_STATUS_S BIT_ULL(56) /* Signaled machine check */
#define MCI_STATUS_AR BIT_ULL(55) /* Action required */
#define MCI_STATUS_TES_MASK GENMASK_ULL(54, 53)
#define MCI_STATUS_TES(s) FIELD_GET(MCI_STATUS_TES_MASK, s)
#define MCI_STATUS_TES_GREEN 1 /* Threshold-based errors below threshold */
#define MCI_STATUS_TES_YELLOW 2 /* Threshold-based errors above threshold */
#define MCI_STATUS_CEC_SHIFT 38 /* Corrected Error Count */
#define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
#define MCI_STATUS_CEC(c) (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)

2
arch/x86/include/asm/msr-index.h
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@ -114,6 +114,8 @@
#define MSR_IA32_CORE_CAPS_INTEGRITY_CAPS BIT(MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT)
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT 5
#define MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT BIT(MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT)
#define MSR_IA32_CORE_CAPS_BFF_RESET_BIT 9
#define MSR_IA32_CORE_CAPS_BFF_RESET BIT(MSR_IA32_CORE_CAPS_BFF_RESET_BIT)
#define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
#define NHM_C3_AUTO_DEMOTE (1UL << 25)