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arm64: dts: qcom: qcs8300: enable pcie0
Add configurations in devicetree for PCIe0, including registers, clocks, interrupts and phy setting sequence. Add PCIe lane equalization preset properties for 8 GT/s and 16GT/s Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251128104928.4070050-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Ziyue Zhang
Bjorn Andersson
parent
8d83fd4f08
commit
46a7c01e7e
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@ -912,7 +912,7 @@ gcc: clock-controller@100000 {
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#power-domain-cells = <1>;
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#power-domain-cells = <1>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&sleep_clk>,
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<&sleep_clk>,
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<0>,
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<&pcie0_phy>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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<0>,
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@ -2264,6 +2264,185 @@ mmss_noc: interconnect@17a0000 {
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qcom,bcm-voters = <&apps_bcm_voter>;
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qcom,bcm-voters = <&apps_bcm_voter>;
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};
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};
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pcie0: pci@1c00000 {
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device_type = "pci";
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compatible = "qcom,pcie-qcs8300", "qcom,pcie-sa8775p";
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reg = <0x0 0x01c00000 0x0 0x3000>,
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<0x0 0x40000000 0x0 0xf20>,
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<0x0 0x40000f20 0x0 0xa8>,
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<0x0 0x40001000 0x0 0x4000>,
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<0x0 0x40100000 0x0 0x100000>,
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<0x0 0x01c03000 0x0 0x1000>;
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reg-names = "parf",
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"dbi",
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"elbi",
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"atu",
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"config",
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"mhi";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
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<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
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bus-range = <0x00 0xff>;
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dma-coherent;
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linux,pci-domain = <0>;
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num-lanes = <2>;
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interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0",
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"msi1",
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"msi2",
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"msi3",
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"msi4",
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"msi5",
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"msi6",
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"msi7",
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"global";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &intc GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &intc GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &intc GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
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<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
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clock-names = "aux",
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"cfg",
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"bus_master",
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"bus_slave",
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"slave_q2a";
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assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
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assigned-clock-rates = <19200000>;
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interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "pcie-mem",
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"cpu-pcie";
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iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
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<0x100 &pcie_smmu 0x0001 0x1>;
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resets = <&gcc GCC_PCIE_0_BCR>,
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<&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
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reset-names = "pci",
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"link_down";
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power-domains = <&gcc GCC_PCIE_0_GDSC>;
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eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
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eq-presets-16gts = /bits/ 8 <0x55 0x55>;
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operating-points-v2 = <&pcie0_opp_table>;
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status = "disabled";
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pcie0_opp_table: opp-table {
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compatible = "operating-points-v2";
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/* GEN 1 x1 */
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opp-2500000 {
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opp-hz = /bits/ 64 <2500000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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opp-peak-kBps = <250000 1>;
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};
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/* GEN 1 x2 and GEN 2 x1 */
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opp-5000000 {
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opp-hz = /bits/ 64 <5000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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opp-peak-kBps = <500000 1>;
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};
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/* GEN 2 x2 */
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opp-10000000 {
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opp-hz = /bits/ 64 <10000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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opp-peak-kBps = <1000000 1>;
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};
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/* GEN 3 x1 */
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opp-8000000 {
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opp-hz = /bits/ 64 <8000000>;
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required-opps = <&rpmhpd_opp_svs_l1>;
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opp-peak-kBps = <984500 1>;
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};
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/* GEN 3 x2 and GEN 4 x1 */
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opp-16000000 {
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opp-hz = /bits/ 64 <16000000>;
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required-opps = <&rpmhpd_opp_nom>;
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opp-peak-kBps = <1969000 1>;
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};
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/* GEN 4 x2 */
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opp-32000000 {
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opp-hz = /bits/ 64 <32000000>;
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required-opps = <&rpmhpd_opp_nom>;
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opp-peak-kBps = <3938000 1>;
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};
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};
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pcieport0: pcie@0 {
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device_type = "pci";
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reg = <0x0 0x0 0x0 0x0 0x0>;
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bus-range = <0x01 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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phys = <&pcie0_phy>;
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};
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};
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pcie0_phy: phy@1c04000 {
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compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy";
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reg = <0x0 0x01c04000 0x0 0x2000>;
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clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_EN>,
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<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
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<&gcc GCC_PCIE_0_PIPE_CLK>,
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<&gcc GCC_PCIE_0_PIPEDIV2_CLK>;
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clock-names = "aux",
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"cfg_ahb",
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"ref",
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"rchng",
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"pipe",
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"pipediv2";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "phy";
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assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
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assigned-clock-rates = <100000000>;
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#clock-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk";
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#phy-cells = <0>;
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status = "disabled";
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};
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ufs_mem_hc: ufs@1d84000 {
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ufs_mem_hc: ufs@1d84000 {
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compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
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compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
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reg = <0x0 0x01d84000 0x0 0x3000>;
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reg = <0x0 0x01d84000 0x0 0x3000>;
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