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drm/panel: himax-hx8394: transition to mipi_dsi wrapped functions
Changes the himax-hx8394 panel to use multi style functions for improved error handling. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Tejas Vipin <tejasvipin76@gmail.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20250325094707.961349-1-tejasvipin76@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
This commit is contained in:
Tejas Vipin
Dmitry Baryshkov
parent
20e8219205
commit
4658f363fe
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@ -80,7 +80,7 @@ struct hx8394_panel_desc {
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unsigned int lanes;
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unsigned long mode_flags;
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enum mipi_dsi_pixel_format format;
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int (*init_sequence)(struct hx8394 *ctx);
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void (*init_sequence)(struct mipi_dsi_multi_context *dsi_ctx);
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};
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static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel)
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@ -88,98 +88,94 @@ static inline struct hx8394 *panel_to_hx8394(struct drm_panel *panel)
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return container_of(panel, struct hx8394, panel);
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}
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static int hsd060bhw4_init_sequence(struct hx8394 *ctx)
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static void hsd060bhw4_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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/* 5.19.8 SETEXTC: Set extension command (B9h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
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0xff, 0x83, 0x94);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,
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0xff, 0x83, 0x94);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x48, 0x11, 0x71, 0x09, 0x32, 0x24, 0x71, 0x31, 0x55, 0x30);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
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0x48, 0x11, 0x71, 0x09, 0x32, 0x24, 0x71, 0x31, 0x55, 0x30);
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/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
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0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,
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0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
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/* 5.19.3 SETDISP: Set display related register (B2h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
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0x00, 0x80, 0x78, 0x0c, 0x07);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,
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0x00, 0x80, 0x78, 0x0c, 0x07);
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/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
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0x12, 0x63, 0x12, 0x63, 0x12, 0x63, 0x01, 0x0c, 0x7c, 0x55,
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0x00, 0x3f, 0x12, 0x6b, 0x12, 0x6b, 0x12, 0x6b, 0x01, 0x0c,
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0x7c);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,
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0x12, 0x63, 0x12, 0x63, 0x12, 0x63, 0x01, 0x0c, 0x7c, 0x55,
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0x00, 0x3f, 0x12, 0x6b, 0x12, 0x6b, 0x12, 0x6b, 0x01, 0x0c,
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0x7c);
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/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
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0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, 0x00, 0x00, 0x32, 0x10,
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0x09, 0x00, 0x09, 0x32, 0x15, 0xad, 0x05, 0xad, 0x32, 0x00,
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0x00, 0x00, 0x00, 0x37, 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00,
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0x00, 0x0c, 0x40);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,
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0x00, 0x00, 0x00, 0x00, 0x3c, 0x1c, 0x00, 0x00, 0x32, 0x10,
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0x09, 0x00, 0x09, 0x32, 0x15, 0xad, 0x05, 0xad, 0x32, 0x00,
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0x00, 0x00, 0x00, 0x37, 0x03, 0x0b, 0x0b, 0x37, 0x00, 0x00,
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0x00, 0x0c, 0x40);
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/* 5.19.20 Set GIP Option1 (D5h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
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0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x01,
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0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,
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0x19, 0x19, 0x18, 0x18, 0x1b, 0x1b, 0x1a, 0x1a, 0x00, 0x01,
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0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x24, 0x25, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
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/* 5.19.21 Set GIP Option2 (D6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
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0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, 0x1a, 0x1a, 0x07, 0x06,
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0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x25, 0x24, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,
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0x18, 0x18, 0x19, 0x19, 0x1b, 0x1b, 0x1a, 0x1a, 0x07, 0x06,
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0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x25, 0x24, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18);
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/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
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0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, 0x1a, 0x18, 0x31, 0x3f,
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0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a,
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0x99, 0x4a, 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00,
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0x04, 0x0c, 0x11, 0x13, 0x17, 0x1a, 0x18, 0x31,
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0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f,
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0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, 0x4b,
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0x4a, 0x4c, 0x4b, 0x7f);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,
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0x00, 0x04, 0x0c, 0x12, 0x14, 0x18, 0x1a, 0x18, 0x31, 0x3f,
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0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f, 0x82, 0x7e, 0x8a,
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0x99, 0x4a, 0x48, 0x49, 0x4b, 0x4a, 0x4c, 0x4b, 0x7f, 0x00,
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0x04, 0x0c, 0x11, 0x13, 0x17, 0x1a, 0x18, 0x31,
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0x3f, 0x4d, 0x4c, 0x54, 0x65, 0x6b, 0x70, 0x7f,
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0x82, 0x7e, 0x8a, 0x99, 0x4a, 0x48, 0x49, 0x4b,
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0x4a, 0x4c, 0x4b, 0x7f);
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/* 5.19.17 SETPANEL (CCh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
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0x0b);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,
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0x0b);
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/* Unknown command, not listed in the HX8394-F datasheet */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
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0x1f, 0x31);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,
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0x1f, 0x31);
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/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
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0x7d, 0x7d);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,
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0x7d, 0x7d);
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/* Unknown command, not listed in the HX8394-F datasheet */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
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0x02);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,
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0x02);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x01);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
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0x01);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
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0x00);
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/* 5.19.11 Set register bank (BDh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
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0x00);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
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0x00);
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/* Unknown command, not listed in the HX8394-F datasheet */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
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0xed);
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return 0;
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,
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0xed);
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}
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static const struct drm_display_mode hsd060bhw4_mode = {
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@ -205,114 +201,110 @@ static const struct hx8394_panel_desc hsd060bhw4_desc = {
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.init_sequence = hsd060bhw4_init_sequence,
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};
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static int powkiddy_x55_init_sequence(struct hx8394 *ctx)
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static void powkiddy_x55_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
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{
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struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
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/* 5.19.8 SETEXTC: Set extension command (B9h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
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0xff, 0x83, 0x94);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,
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0xff, 0x83, 0x94);
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/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
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0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,
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0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
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/* 5.19.2 SETPOWER: Set power (B1h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
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0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57, 0x47);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
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0x48, 0x12, 0x72, 0x09, 0x32, 0x54, 0x71, 0x71, 0x57, 0x47);
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/* 5.19.3 SETDISP: Set display related register (B2h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
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0x00, 0x80, 0x64, 0x2c, 0x16, 0x2f);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,
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0x00, 0x80, 0x64, 0x2c, 0x16, 0x2f);
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/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
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0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 0x86, 0x75,
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0x00, 0x3f, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c,
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0x86);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,
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0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c, 0x86, 0x75,
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0x00, 0x3f, 0x73, 0x74, 0x73, 0x74, 0x73, 0x74, 0x01, 0x0c,
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0x86);
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/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
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0x6e, 0x6e);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,
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0x6e, 0x6e);
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/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
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0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0c, 0x00, 0x08, 0x10,
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0x08, 0x00, 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 0x02, 0x15,
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0x06, 0x05, 0x06, 0x47, 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
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0x07, 0x0c, 0x40);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,
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0x00, 0x00, 0x07, 0x07, 0x40, 0x07, 0x0c, 0x00, 0x08, 0x10,
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0x08, 0x00, 0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a, 0x02, 0x15,
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0x06, 0x05, 0x06, 0x47, 0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
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0x07, 0x0c, 0x40);
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/* 5.19.20 Set GIP Option1 (D5h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
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0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 0x18, 0x18,
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0x26, 0x27, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,
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0x18, 0x18, 0x18, 0x18);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,
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0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25, 0x18, 0x18,
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0x26, 0x27, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21,
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0x18, 0x18, 0x18, 0x18);
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/* 5.19.21 Set GIP Option2 (D6h) */
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mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
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0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
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0x01, 0x00, 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18,
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0x27, 0x26, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
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0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24,
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0x18, 0x18, 0x18, 0x18);
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mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,
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0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02,
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0x01, 0x00, 0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20, 0x18, 0x18,
|
||||
0x27, 0x26, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x25, 0x24,
|
||||
0x18, 0x18, 0x18, 0x18);
|
||||
|
||||
/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
|
||||
0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56,
|
||||
0x65, 0x66, 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, 0x98, 0xa8,
|
||||
0xb9, 0x5d, 0x5c, 0x61, 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00,
|
||||
0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56, 0x65,
|
||||
0x65, 0x6e, 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, 0xa8, 0xba,
|
||||
0x5d, 0x5d, 0x62, 0x67, 0x6b, 0x72, 0x7f, 0x7f);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,
|
||||
0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56,
|
||||
0x65, 0x66, 0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d, 0x98, 0xa8,
|
||||
0xb9, 0x5d, 0x5c, 0x61, 0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00,
|
||||
0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24, 0x22, 0x47, 0x56, 0x65,
|
||||
0x65, 0x6e, 0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99, 0xa8, 0xba,
|
||||
0x5d, 0x5d, 0x62, 0x67, 0x6b, 0x72, 0x7f, 0x7f);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
|
||||
0x1f, 0x31);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,
|
||||
0x1f, 0x31);
|
||||
|
||||
/* 5.19.17 SETPANEL (CCh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
|
||||
0x0b);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,
|
||||
0x0b);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
|
||||
0x02);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,
|
||||
0x02);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x02);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x02);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x01);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x01);
|
||||
|
||||
/* 5.19.2 SETPOWER: Set power (B1h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
|
||||
0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
|
||||
0x00);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN5,
|
||||
0x40, 0x81, 0x50, 0x00, 0x1a, 0xfc, 0x01);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN5,
|
||||
0x40, 0x81, 0x50, 0x00, 0x1a, 0xfc, 0x01);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2,
|
||||
0xed);
|
||||
|
||||
return 0;
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2,
|
||||
0xed);
|
||||
}
|
||||
|
||||
static const struct drm_display_mode powkiddy_x55_mode = {
|
||||
|
|
@ -339,131 +331,127 @@ static const struct hx8394_panel_desc powkiddy_x55_desc = {
|
|||
.init_sequence = powkiddy_x55_init_sequence,
|
||||
};
|
||||
|
||||
static int mchp_ac40t08a_init_sequence(struct hx8394 *ctx)
|
||||
static void mchp_ac40t08a_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
|
||||
{
|
||||
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
|
||||
/* DCS commands do not seem to be sent correclty without this delay */
|
||||
msleep(20);
|
||||
mipi_dsi_msleep(dsi_ctx, 20);
|
||||
|
||||
/* 5.19.8 SETEXTC: Set extension command (B9h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETEXTC,
|
||||
0xff, 0x83, 0x94);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETEXTC,
|
||||
0xff, 0x83, 0x94);
|
||||
|
||||
/* 5.19.9 SETMIPI: Set MIPI control (BAh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETMIPI,
|
||||
0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETMIPI,
|
||||
0x63, 0x03, 0x68, 0x6b, 0xb2, 0xc0);
|
||||
|
||||
/* 5.19.2 SETPOWER: Set power (B1h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
|
||||
0x48, 0x12, 0x72, 0x09, 0x32, 0x54,
|
||||
0x71, 0x71, 0x57, 0x47);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
|
||||
0x48, 0x12, 0x72, 0x09, 0x32, 0x54,
|
||||
0x71, 0x71, 0x57, 0x47);
|
||||
|
||||
/* 5.19.3 SETDISP: Set display related register (B2h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETDISP,
|
||||
0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETDISP,
|
||||
0x00, 0x80, 0x64, 0x0c, 0x0d, 0x2f);
|
||||
|
||||
/* 5.19.4 SETCYC: Set display waveform cycles (B4h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCYC,
|
||||
0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
|
||||
0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f,
|
||||
0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
|
||||
0x01, 0x0c, 0x86);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCYC,
|
||||
0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
|
||||
0x01, 0x0c, 0x86, 0x75, 0x00, 0x3f,
|
||||
0x73, 0x74, 0x73, 0x74, 0x73, 0x74,
|
||||
0x01, 0x0c, 0x86);
|
||||
|
||||
/* 5.19.5 SETVCOM: Set VCOM voltage (B6h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETVCOM,
|
||||
0x6e, 0x6e);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETVCOM,
|
||||
0x6e, 0x6e);
|
||||
|
||||
/* 5.19.19 SETGIP0: Set GIP Option0 (D3h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP0,
|
||||
0x00, 0x00, 0x07, 0x07, 0x40, 0x07,
|
||||
0x0c, 0x00, 0x08, 0x10, 0x08, 0x00,
|
||||
0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a,
|
||||
0x02, 0x15, 0x06, 0x05, 0x06, 0x47,
|
||||
0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
|
||||
0x07, 0x0c, 0x40);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP0,
|
||||
0x00, 0x00, 0x07, 0x07, 0x40, 0x07,
|
||||
0x0c, 0x00, 0x08, 0x10, 0x08, 0x00,
|
||||
0x08, 0x54, 0x15, 0x0a, 0x05, 0x0a,
|
||||
0x02, 0x15, 0x06, 0x05, 0x06, 0x47,
|
||||
0x44, 0x0a, 0x0a, 0x4b, 0x10, 0x07,
|
||||
0x07, 0x0c, 0x40);
|
||||
|
||||
/* 5.19.20 Set GIP Option1 (D5h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP1,
|
||||
0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01,
|
||||
0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
|
||||
0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25,
|
||||
0x18, 0x18, 0x26, 0x27, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x20, 0x21, 0x18, 0x18,
|
||||
0x18, 0x18);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP1,
|
||||
0x1c, 0x1c, 0x1d, 0x1d, 0x00, 0x01,
|
||||
0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
|
||||
0x08, 0x09, 0x0a, 0x0b, 0x24, 0x25,
|
||||
0x18, 0x18, 0x26, 0x27, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x20, 0x21, 0x18, 0x18,
|
||||
0x18, 0x18);
|
||||
|
||||
/* 5.19.21 Set GIP Option2 (D6h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGIP2,
|
||||
0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06,
|
||||
0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
|
||||
0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20,
|
||||
0x18, 0x18, 0x27, 0x26, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x25, 0x24, 0x18, 0x18,
|
||||
0x18, 0x18);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGIP2,
|
||||
0x1c, 0x1c, 0x1d, 0x1d, 0x07, 0x06,
|
||||
0x05, 0x04, 0x03, 0x02, 0x01, 0x00,
|
||||
0x0b, 0x0a, 0x09, 0x08, 0x21, 0x20,
|
||||
0x18, 0x18, 0x27, 0x26, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
|
||||
0x18, 0x18, 0x25, 0x24, 0x18, 0x18,
|
||||
0x18, 0x18);
|
||||
|
||||
/* 5.19.25 SETGAMMA: Set gamma curve related setting (E0h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETGAMMA,
|
||||
0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21,
|
||||
0x24, 0x22, 0x47, 0x56, 0x65, 0x66,
|
||||
0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d,
|
||||
0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61,
|
||||
0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00,
|
||||
0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24,
|
||||
0x22, 0x47, 0x56, 0x65, 0x65, 0x6e,
|
||||
0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99,
|
||||
0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67,
|
||||
0x6b, 0x72, 0x7f, 0x7f);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETGAMMA,
|
||||
0x00, 0x0a, 0x15, 0x1b, 0x1e, 0x21,
|
||||
0x24, 0x22, 0x47, 0x56, 0x65, 0x66,
|
||||
0x6e, 0x82, 0x88, 0x8b, 0x9a, 0x9d,
|
||||
0x98, 0xa8, 0xb9, 0x5d, 0x5c, 0x61,
|
||||
0x66, 0x6a, 0x6f, 0x7f, 0x7f, 0x00,
|
||||
0x0a, 0x15, 0x1b, 0x1e, 0x21, 0x24,
|
||||
0x22, 0x47, 0x56, 0x65, 0x65, 0x6e,
|
||||
0x81, 0x87, 0x8b, 0x98, 0x9d, 0x99,
|
||||
0xa8, 0xba, 0x5d, 0x5d, 0x62, 0x67,
|
||||
0x6b, 0x72, 0x7f, 0x7f);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet (C0H) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN1,
|
||||
0x1f, 0x73);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN1,
|
||||
0x1f, 0x73);
|
||||
|
||||
/* Set CABC control (C9h)*/
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETCABC,
|
||||
0x76, 0x00, 0x30);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETCABC,
|
||||
0x76, 0x00, 0x30);
|
||||
|
||||
/* 5.19.17 SETPANEL (CCh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPANEL,
|
||||
0x0b);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPANEL,
|
||||
0x0b);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet (D4h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN3,
|
||||
0x02);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN3,
|
||||
0x02);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x02);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x02);
|
||||
|
||||
/* 5.19.11 Set register bank (D8h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN4,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN4,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x01);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x01);
|
||||
|
||||
/* 5.19.2 SETPOWER: Set power (B1h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETPOWER,
|
||||
0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETPOWER,
|
||||
0x00);
|
||||
|
||||
/* 5.19.11 Set register bank (BDh) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_SETREGBANK,
|
||||
0x00);
|
||||
|
||||
/* Unknown command, not listed in the HX8394-F datasheet (C6h) */
|
||||
mipi_dsi_dcs_write_seq(dsi, HX8394_CMD_UNKNOWN2,
|
||||
0xed);
|
||||
|
||||
return 0;
|
||||
mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX8394_CMD_UNKNOWN2,
|
||||
0xed);
|
||||
}
|
||||
|
||||
static const struct drm_display_mode mchp_ac40t08a_mode = {
|
||||
|
|
@ -493,35 +481,31 @@ static int hx8394_enable(struct drm_panel *panel)
|
|||
{
|
||||
struct hx8394 *ctx = panel_to_hx8394(panel);
|
||||
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
|
||||
int ret;
|
||||
|
||||
ret = ctx->desc->init_sequence(ctx);
|
||||
if (ret) {
|
||||
dev_err(ctx->dev, "Panel init sequence failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ctx->desc->init_sequence(&dsi_ctx);
|
||||
|
||||
ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
|
||||
if (ret) {
|
||||
dev_err(ctx->dev, "Failed to exit sleep mode: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
|
||||
|
||||
if (dsi_ctx.accum_err)
|
||||
return dsi_ctx.accum_err;
|
||||
/* Panel is operational 120 msec after reset */
|
||||
msleep(120);
|
||||
|
||||
ret = mipi_dsi_dcs_set_display_on(dsi);
|
||||
if (ret) {
|
||||
dev_err(ctx->dev, "Failed to turn on the display: %d\n", ret);
|
||||
mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
|
||||
if (dsi_ctx.accum_err)
|
||||
goto sleep_in;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
sleep_in:
|
||||
ret = dsi_ctx.accum_err;
|
||||
dsi_ctx.accum_err = 0;
|
||||
|
||||
/* This will probably fail, but let's try orderly power off anyway. */
|
||||
if (!mipi_dsi_dcs_enter_sleep_mode(dsi))
|
||||
msleep(50);
|
||||
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
|
||||
mipi_dsi_msleep(&dsi_ctx, 50);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -530,17 +514,12 @@ static int hx8394_disable(struct drm_panel *panel)
|
|||
{
|
||||
struct hx8394 *ctx = panel_to_hx8394(panel);
|
||||
struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
|
||||
int ret;
|
||||
struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
|
||||
|
||||
ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
|
||||
if (ret) {
|
||||
dev_err(ctx->dev, "Failed to enter sleep mode: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
|
||||
mipi_dsi_msleep(&dsi_ctx, 50); /* about 3 frames */
|
||||
|
||||
msleep(50); /* about 3 frames */
|
||||
|
||||
return 0;
|
||||
return dsi_ctx.accum_err;
|
||||
}
|
||||
|
||||
static int hx8394_unprepare(struct drm_panel *panel)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user