mirror of
https://github.com/torvalds/linux.git
synced 2026-06-04 12:35:52 +02:00
mvebu dt64 for 6.11 (part 1)
armada-3720: align GPIO keys and LED node namee with bindings Add description for solidrun cn9130 som and clearfog boards -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCZofxAQAKCRALBhiOFHI7 1a61AJwI37rg/Ki0O1OPKCfkdgrmHIIRoQCfR7rhEmu5lzgC5CwAcQhdtiEjSB4= =ONUU -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmaL+b0ACgkQYKtH/8kJ UidsFRAAnTaU5h/IsjYky4vOwtm+p2OoxbnOEAHzRySiJ8nAIZcYnm3i45tJK7Yt XzTRhDo1li3EpXgL+n4AZb4dY08c2dquoRky/7zSZnKV5XMhP6Oxzka3EwDq4i/s qpaMD5v22McpqbX+/y0eP0Ja7Bi5pbVQw5u+TpNqEb4NNVY38OXizREQZa0Pi3VX a/jqFCLNA9BCSZYDkFXjgToaoVnzfMfX0762DJqDoE3jE5ZUN3QWQMoCT6mx6aoD rdx9pmjELl3gtXkX+RHggfuHYiQOR/EwhscqpPQsLBUCyOzKsEXWsj4AJiBlTIqd dXLLLUfa5XZpQSJ0vOJzDGRbXJYxrHHL3cZBsJKpxN68ZMtWrCBO9UYUT4yAphvI FwFJv7adNvy65yCW0fFlIGXp3rNkG5day9rPo+2ENEIl4tACIADZD1O+EZf0ivYL 1RFEb01OCsdJOsIlmOMIQ3NjAtwLJHBENm7+ctA7jNs4DLKyJp5SOnDVLqYinuF+ 6oDznE4upreB9ErBdejoP8bQKMsP7qwbbzg8YCsMwD3+aO/6fPrpiBlJBpMgT+4x VGQH0EuTe9XyPSbVosVfWR7wK083sQXMyDHWUwHrUj3oYdYf8Ux/CO690Teo/r2A 2WAEaZT67Wraf451/kLlPWUsosgxCCPkZnc+gAVfLZxCqCua1qk= =XffQ -----END PGP SIGNATURE----- Merge tag 'mvebu-dt64-6.11-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt mvebu dt64 for 6.11 (part 1) armada-3720: align GPIO keys and LED node namee with bindings Add description for solidrun cn9130 som and clearfog boards * tag 'mvebu-dt64-6.11-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: add description for solidrun cn9132 cex7 module and clearfog board arm64: dts: add description for solidrun cn9131 solidwan board arm64: dts: add description for solidrun cn9130 som and clearfog boards dt-bindings: arm64: marvell: add solidrun cn9132 CEX-7 evaluation board dt-bindings: arm64: marvell: add solidrun cn9130 som based boards arm64: dts: armada-3720: align LED node name with bindings arm64: dts: armada-3720: align GPIO keys node name with bindings Link: https://lore.kernel.org/r/87wmlzixln.fsf@BLaptop.bootlin.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
462eeb978d
|
|
@ -82,4 +82,22 @@ properties:
|
|||
- const: marvell,armada-ap807-quad
|
||||
- const: marvell,armada-ap807
|
||||
|
||||
- description:
|
||||
SolidRun CN9130 SoM based single-board computers
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,cn9130-clearfog-base
|
||||
- solidrun,cn9130-clearfog-pro
|
||||
- solidrun,cn9131-solidwan
|
||||
- const: solidrun,cn9130-sr-som
|
||||
- const: marvell,cn9130
|
||||
|
||||
- description:
|
||||
SolidRun CN9132 COM-Express Type 7 based single-board computers
|
||||
items:
|
||||
- enum:
|
||||
- solidrun,cn9132-clearfog
|
||||
- const: solidrun,cn9132-sr-cex7
|
||||
- const: marvell,cn9130
|
||||
|
||||
additionalProperties: true
|
||||
|
|
|
|||
|
|
@ -28,3 +28,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
|
|||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += ac5x-rd-carrier-cn9131.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-base.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-cf-pro.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-cf-solidwan.dtb
|
||||
dtb-$(CONFIG_ARCH_MVEBU) += cn9132-clearfog.dtb
|
||||
|
|
|
|||
|
|
@ -41,7 +41,7 @@ vcc_sd_reg1: regulator {
|
|||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
button-reset {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpionb 14 GPIO_ACTIVE_LOW>;
|
||||
|
|
@ -57,17 +57,17 @@ switch {
|
|||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
vpn {
|
||||
led-vpn {
|
||||
label = "green:vpn";
|
||||
gpios = <&gpionb 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wan {
|
||||
led-wan {
|
||||
label = "green:wan";
|
||||
gpios = <&gpionb 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led_power: power {
|
||||
led_power: led-power {
|
||||
label = "green:power";
|
||||
gpios = <&gpionb 13 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
|
|
|
|||
178
arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
Normal file
178
arch/arm64/boot/dts/marvell/cn9130-cf-base.dts
Normal file
|
|
@ -0,0 +1,178 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* DTS for SolidRun CN9130 Clearfog Base.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
#include "cn9130.dtsi"
|
||||
#include "cn9130-sr-som.dtsi"
|
||||
#include "cn9130-cf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 Clearfog Base";
|
||||
compatible = "solidrun,cn9130-clearfog-base",
|
||||
"solidrun,cn9130-sr-som", "marvell,cn9130";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&rear_button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button-0 {
|
||||
/* The rear SW3 button */
|
||||
label = "Rear Button";
|
||||
gpios = <&cp0_gpio1 31 GPIO_ACTIVE_LOW>;
|
||||
linux,can-disable;
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
};
|
||||
|
||||
rfkill-m2-gnss {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "m.2 GNSS";
|
||||
radio-type = "gps";
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&expander0 9 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* M.2 is B-keyed, so w-disable is for WWAN */
|
||||
rfkill-m2-wwan {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "m.2 WWAN";
|
||||
radio-type = "wwan";
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #3 - SGMII 1GE */
|
||||
&cp0_eth1 {
|
||||
phy = <&phy1>;
|
||||
phys = <&cp0_comphy3 1>;
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth2_phy {
|
||||
/*
|
||||
* Configure LEDs default behaviour:
|
||||
* - LED[0]: link/activity: On/blink (green)
|
||||
* - LED[1]: link is 100/1000Mbps: On (yellow)
|
||||
* - LED[2]: high impedance (floating)
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a61>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_gpio1 {
|
||||
sim-select-hog {
|
||||
gpio-hog;
|
||||
gpios = <27 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "sim-select";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
/*
|
||||
* Configure LEDs default behaviour:
|
||||
* - LED[0]: link/activity: On/blink (green)
|
||||
* - LED[1]: link is 100/1000Mbps: On (yellow)
|
||||
* - LED[2]: high impedance (floating)
|
||||
*
|
||||
* Configure LEDs electrical polarity
|
||||
* - on-state: low
|
||||
* - off-state: high (not hi-z, to avoid residual glow)
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a61>,
|
||||
<3 17 0x003f 0x000a>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
pinctrl-0 = <&sim_select_pins>;
|
||||
pintrl-names = "default";
|
||||
|
||||
rear_button_pins: cp0-rear-button-pins {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sim_select_pins: cp0-sim-select-pins {
|
||||
marvell,pins = "mpp27";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* SRDS #4 - USB 3.0 host on M.2 connector
|
||||
* USB-2.0 Host on Type-A connector
|
||||
*/
|
||||
&cp0_usb3_1 {
|
||||
phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
|
||||
phy-names = "comphy", "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&expander0 {
|
||||
m2-full-card-power-off-hog {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "m2-full-card-power-off";
|
||||
};
|
||||
|
||||
m2-reset-hog {
|
||||
gpio-hog;
|
||||
gpios = <10 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "m2-reset";
|
||||
};
|
||||
};
|
||||
375
arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
Normal file
375
arch/arm64/boot/dts/marvell/cn9130-cf-pro.dts
Normal file
|
|
@ -0,0 +1,375 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* DTS for SolidRun CN9130 Clearfog Pro.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
#include "cn9130.dtsi"
|
||||
#include "cn9130-sr-som.dtsi"
|
||||
#include "cn9130-cf.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 Clearfog Pro";
|
||||
compatible = "solidrun,cn9130-clearfog-pro",
|
||||
"solidrun,cn9130-sr-som", "marvell,cn9130";
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&rear_button_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button-0 {
|
||||
/* The rear SW3 button */
|
||||
label = "Rear Button";
|
||||
gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
linux,can-disable;
|
||||
linux,code = <BTN_0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #3 - SGMII 1GE to L2 switch */
|
||||
&cp0_eth1 {
|
||||
phys = <&cp0_comphy3 1>;
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_eth2_phy {
|
||||
/*
|
||||
* Configure LEDs default behaviour similar to switch ports:
|
||||
* - LED[0]: link/activity: On/blink (green)
|
||||
* - LED[1]: link is 100/1000Mbps: On (red)
|
||||
* - LED[2]: high impedance (floating)
|
||||
*
|
||||
* Switch port defaults:
|
||||
* - LED0: link/activity: On/blink (green)
|
||||
* - LED1: link is 1000Mbps: On (red)
|
||||
*
|
||||
* Identical configuration is impossible with hardware offload.
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a61>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
label = "LED2";
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_WAN;
|
||||
label = "LED1";
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <4>;
|
||||
pinctrl-0 = <&dsa_clk_pins &dsa_pins>;
|
||||
pinctrl-names = "default";
|
||||
reset-gpios = <&cp0_gpio1 27 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet-port@0 {
|
||||
reg = <0>;
|
||||
label = "lan5";
|
||||
phy = <&switch0phy0>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED12";
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED11";
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan4";
|
||||
phy = <&switch0phy1>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED10";
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED9";
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan3";
|
||||
phy = <&switch0phy2>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED8";
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED7";
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan2";
|
||||
phy = <&switch0phy3>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED6";
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED5";
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan1";
|
||||
phy = <&switch0phy4>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED4";
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
label = "LED3";
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&cp0_eth1>;
|
||||
phy-mode = "sgmii";
|
||||
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@6 {
|
||||
reg = <6>;
|
||||
label = "lan6";
|
||||
phy-mode = "rgmii";
|
||||
|
||||
/*
|
||||
* Because of mdio address conflict the
|
||||
* external phy is not readable.
|
||||
* Force a fixed link instead.
|
||||
*/
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch0phy0: ethernet-phy@0 {
|
||||
reg = <0x0>;
|
||||
};
|
||||
|
||||
switch0phy1: ethernet-phy@1 {
|
||||
reg = <0x1>;
|
||||
/*
|
||||
* Indirectly configure default behaviour
|
||||
* for port lan6 leds behind external phy.
|
||||
* Internal PHYs are not using page 3,
|
||||
* therefore writing to it is safe.
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a61>;
|
||||
};
|
||||
|
||||
switch0phy2: ethernet-phy@2 {
|
||||
reg = <0x2>;
|
||||
};
|
||||
|
||||
switch0phy3: ethernet-phy@3 {
|
||||
reg = <0x3>;
|
||||
};
|
||||
|
||||
switch0phy4: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* There is an external phy on the switch mdio bus.
|
||||
* Because its mdio address collides with internal phys,
|
||||
* it is not readable.
|
||||
*
|
||||
* mdio-external {
|
||||
* compatible = "marvell,mv88e6xxx-mdio-external";
|
||||
* #address-cells = <1>;
|
||||
* #size-cells = <0>;
|
||||
*
|
||||
* ethernet-phy@1 {
|
||||
* reg = <0x1>;
|
||||
* };
|
||||
* };
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #4 - miniPCIe (CON2) */
|
||||
&cp0_pcie1 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp0_comphy4 1>;
|
||||
/* dw-pcie inverts internally */
|
||||
reset-gpios = <&expander0 2 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
dsa_clk_pins: cp0-dsa-clk-pins {
|
||||
marvell,pins = "mpp40";
|
||||
marvell,function = "synce1";
|
||||
};
|
||||
|
||||
dsa_pins: cp0-dsa-pins {
|
||||
marvell,pins = "mpp27", "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
rear_button_pins: cp0-rear-button-pins {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
/* add pin for chip-select 1 on mikrobus */
|
||||
pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
|
||||
};
|
||||
|
||||
/* USB-2.0 Host on Type-A connector */
|
||||
&cp0_usb3_1 {
|
||||
phys = <&cp0_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&expander0 {
|
||||
/* CON2 */
|
||||
pcie1-0-clkreq-hog {
|
||||
gpio-hog;
|
||||
gpios = <4 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "pcie1.0-clkreq";
|
||||
};
|
||||
|
||||
/* CON2 */
|
||||
pcie1-0-w-disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <7 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie1.0-w-disable";
|
||||
};
|
||||
};
|
||||
197
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
Normal file
197
arch/arm64/boot/dts/marvell/cn9130-cf.dtsi
Normal file
|
|
@ -0,0 +1,197 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* DTS for common base of SolidRun CN9130 Clearfog Base and Pro.
|
||||
*
|
||||
*/
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
/* label nics same order as armada 388 clearfog */
|
||||
ethernet0 = &cp0_eth2;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth0;
|
||||
i2c1 = &cp0_i2c1;
|
||||
mmc1 = &cp0_sdhci0;
|
||||
};
|
||||
|
||||
reg_usb3_vbus0: regulator-usb3-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpios = <&expander0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
sfp: sfp {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&cp0_i2c1>;
|
||||
los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpios = <&expander0 14 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpios = <&expander0 13 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #2 - SFP+ 10GE */
|
||||
&cp0_eth0 {
|
||||
managed = "in-band-status";
|
||||
phys = <&cp0_comphy2 0>;
|
||||
phy-mode = "10gbase-r";
|
||||
sfp = <&sfp>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
expander0: gpio-expander@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
pinctrl-0 = <&expander0_pins>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
/* CON3 */
|
||||
pcie2-0-clkreq-hog {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "pcie2.0-clkreq";
|
||||
};
|
||||
|
||||
/* CON3 */
|
||||
pcie2-0-w-disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie2.0-w-disable";
|
||||
};
|
||||
|
||||
usb3-ilimit-hog {
|
||||
gpio-hog;
|
||||
gpios = <5 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "usb3-current-limit";
|
||||
};
|
||||
|
||||
m2-devslp-hog {
|
||||
gpio-hog;
|
||||
gpios = <11 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "m.2 devslp";
|
||||
};
|
||||
};
|
||||
|
||||
/* The MCP3021 supports standard and fast modes */
|
||||
adc@4c {
|
||||
compatible = "microchip,mcp3021";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
|
||||
carrier_eeprom: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
/*
|
||||
* Routed to SFP, M.2, mikrobus, and miniPCIe
|
||||
* SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
|
||||
* address pins tied low, which takes addresses 0x50 and 0x51.
|
||||
* Mikrobus doesn't specify beyond an I2C bus being present.
|
||||
* PCIe uses ARP to assign addresses, or 0x63-0x64.
|
||||
*/
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - miniPCIe (CON3) */
|
||||
&cp0_pcie2 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp0_comphy5 2>;
|
||||
/* dw-pcie inverts internally */
|
||||
reset-gpios = <&expander0 1 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
cp0_i2c1_pins: cp0-i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
cp0_mmc0_pins: cp0-mmc0-pins {
|
||||
marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
|
||||
mikro_spi_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
mikro_uart_pins: cp0-uart-pins {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "uart1";
|
||||
};
|
||||
|
||||
expander0_pins: cp0-expander0-pins {
|
||||
marvell,pins = "mpp4";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0 - SATA on M.2 connector */
|
||||
&cp0_sata0 {
|
||||
phys = <&cp0_comphy0 1>;
|
||||
status = "okay";
|
||||
|
||||
/* only port 1 is available */
|
||||
/delete-node/ sata-port@0;
|
||||
};
|
||||
|
||||
/* microSD */
|
||||
&cp0_sdhci0 {
|
||||
pinctrl-0 = <&cp0_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
/* CS1 for mikrobus */
|
||||
pinctrl-0 = <&cp0_spi1_pins &mikro_spi_pins>;
|
||||
};
|
||||
|
||||
/*
|
||||
* SRDS #1 - USB-3.0 Host on Type-A connector
|
||||
* USB-2.0 Host on mPCI-e connector (CON3)
|
||||
*/
|
||||
&cp0_usb3_0 {
|
||||
phys = <&cp0_comphy1 0>, <&cp0_utmi0>;
|
||||
phy-names = "comphy", "utmi";
|
||||
vbus-supply = <®_usb3_vbus0>;
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* mikrobus uart */
|
||||
&cp0_uart0 {
|
||||
pinctrl-0 = <&mikro_uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
160
arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
Normal file
160
arch/arm64/boot/dts/marvell/cn9130-sr-som.dtsi
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 SoM";
|
||||
compatible = "solidrun,cn9130-sr-som", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp0_eth1;
|
||||
ethernet2 = &cp0_eth2;
|
||||
i2c0 = &cp0_i2c0;
|
||||
mmc0 = &ap_sdhci0;
|
||||
rtc0 = &cp0_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
v_1_8: regulator-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
/* requires assembly of R9307 */
|
||||
vhv: regulator-vhv-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vhv-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
pinctrl-0 = <&cp0_reg_vhv_pins>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&cp0_gpio2 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ap_pinctrl {
|
||||
ap_mmc0_pins: ap-mmc0-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
|
||||
marvell,function = "sdio";
|
||||
/*
|
||||
* mpp12 is emmc reset, function should be sdio (hw_rst),
|
||||
* but pinctrl-mvebu does not support this.
|
||||
*
|
||||
* From pinctrl-mvebu.h:
|
||||
* "The name will be used to switch to this setting in DT description, e.g.
|
||||
* marvell,function = "uart2". subname is only for debugging purposes."
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
&ap_sdhci0 {
|
||||
bus-width = <8>;
|
||||
pinctrl-0 = <&ap_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
vqmmc-supply = <&v_1_8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* for assembly with phy */
|
||||
&cp0_eth2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_eth2_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy = <&cp0_eth2_phy>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
som_eeprom: eeprom@53 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x53>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
pinctrl-0 = <&cp0_mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
/* assembly option */
|
||||
cp0_eth2_phy: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi1_pins>;
|
||||
/* max speed limited by a mux */
|
||||
spi-max-frequency = <1800000000>;
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/* read command supports max. 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
cp0_eth2_pins: cp0-ge2-rgmii-pins {
|
||||
marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47",
|
||||
"mpp48", "mpp49", "mpp50", "mpp51",
|
||||
"mpp52", "mpp53", "mpp54", "mpp55";
|
||||
/* docs call it "ge2", but cp110-pinctrl "ge1" */
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
cp0_mdio_pins: cp0-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
cp0_spi1_pins: cp0-spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp0_reg_vhv_pins: cp0-reg-vhv-pins {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* AP default console */
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
637
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
Normal file
637
arch/arm64/boot/dts/marvell/cn9131-cf-solidwan.dts
Normal file
|
|
@ -0,0 +1,637 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* DTS for SolidRun CN9130 Clearfog Base.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
#include "cn9130.dtsi"
|
||||
#include "cn9130-sr-som.dtsi"
|
||||
|
||||
/*
|
||||
* Instantiate the external CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp1
|
||||
#define CP11X_BASE f4000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f4600000
|
||||
#define CP11X_PCIE1_BASE f4620000
|
||||
#define CP11X_PCIE2_BASE f4640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9131 SolidWAN";
|
||||
compatible = "solidrun,cn9131-solidwan",
|
||||
"solidrun,cn9130-sr-som", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp1_eth1;
|
||||
ethernet1 = &cp1_eth2;
|
||||
ethernet2 = &cp0_eth1;
|
||||
ethernet3 = &cp0_eth2;
|
||||
ethernet4 = &cp0_eth0;
|
||||
ethernet5 = &cp1_eth0;
|
||||
gpio0 = &ap_gpio;
|
||||
gpio1 = &cp0_gpio1;
|
||||
gpio2 = &cp0_gpio2;
|
||||
gpio3 = &cp1_gpio1;
|
||||
gpio4 = &cp1_gpio2;
|
||||
gpio5 = &expander0;
|
||||
i2c0 = &cp0_i2c0;
|
||||
i2c1 = &cp0_i2c1;
|
||||
i2c2 = &cp1_i2c1;
|
||||
mmc0 = &ap_sdhci0;
|
||||
mmc1 = &cp0_sdhci0;
|
||||
rtc0 = &cp0_rtc;
|
||||
rtc1 = &carrier_rtc;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_led_pins &cp1_led_pins>;
|
||||
|
||||
/* for sfp-1 (J42) */
|
||||
led-sfp1-activity {
|
||||
label = "sfp1:green";
|
||||
gpios = <&cp0_gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* for sfp-1 (J42) */
|
||||
led-sfp1-link {
|
||||
label = "sfp1:yellow";
|
||||
gpios = <&cp0_gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* (J28) */
|
||||
led-sfp0-activity {
|
||||
label = "sfp0:green";
|
||||
gpios = <&cp1_gpio2 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* (J28) */
|
||||
led-sfp0-link {
|
||||
label = "sfp0:yellow";
|
||||
gpios = <&cp1_gpio2 23 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Type-A port on J53 */
|
||||
reg_usb_a_vbus0: regulator-usb-a-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-0 = <&cp0_reg_usb_a_vbus0_pins>;
|
||||
pinctrl-names = "default";
|
||||
regulator-name = "vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpios = <&cp0_gpio1 27 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_usb_a_vbus1: regulator-usb-a-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
pinctrl-0 = <&cp0_reg_usb_a_vbus1_pins>;
|
||||
pinctrl-names = "default";
|
||||
regulator-name = "vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpios = <&cp0_gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sfp0: sfp-0 {
|
||||
compatible = "sff,sfp";
|
||||
pinctrl-0 = <&cp0_sfp0_pins>;
|
||||
pinctrl-names = "default";
|
||||
i2c-bus = <&cp0_i2c1>;
|
||||
los-gpios = <&cp0_gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpios = <&cp0_gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpios = <&cp0_gpio1 31 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <2000>;
|
||||
};
|
||||
|
||||
sfp1: sfp-1 {
|
||||
compatible = "sff,sfp";
|
||||
pinctrl-0 = <&cp1_sfp1_pins>;
|
||||
pinctrl-names = "default";
|
||||
i2c-bus = <&cp1_i2c1>;
|
||||
los-gpios = <&cp1_gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
mod-def0-gpios = <&cp1_gpio2 18 GPIO_ACTIVE_LOW>;
|
||||
tx-disable-gpios = <&cp1_gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
tx-fault-gpios = <&cp1_gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
maximum-power-milliwatt = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #2 - SFP+ 10GE */
|
||||
&cp0_eth0 {
|
||||
managed = "in-band-status";
|
||||
phy-mode = "10gbase-r";
|
||||
phys = <&cp0_comphy2 0>;
|
||||
sfp = <&sfp0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #3 - SGMII 1GE */
|
||||
&cp0_eth1 {
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
/* Without mdio phy access rely on sgmii auto-negotiation. */
|
||||
phys = <&cp0_comphy3 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #1 - SGMII */
|
||||
&cp0_eth2 {
|
||||
/delete-property/ pinctrl-0;
|
||||
/delete-property/ pinctrl-names;
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
phy = <&cp0_phy1>;
|
||||
phys = <&cp0_comphy1 2>;
|
||||
};
|
||||
|
||||
&cp0_gpio1 {
|
||||
pcie0-0-w-disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <6 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "pcie0.0-w-disable";
|
||||
};
|
||||
|
||||
/* J34 */
|
||||
m2-full-card-power-off-hog {
|
||||
gpio-hog;
|
||||
gpios = <8 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "m2-full-card-power-off";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
/* assembly option */
|
||||
fan-controller@18 {
|
||||
compatible = "ti,amc6821";
|
||||
reg = <0x18>;
|
||||
};
|
||||
|
||||
expander0: gpio@41 {
|
||||
compatible = "nxp,pca9536";
|
||||
reg = <0x41>;
|
||||
|
||||
usb-a-vbus0-ilimit-hog {
|
||||
gpio-hog;
|
||||
gpios = <0 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "vbus0-ilimit";
|
||||
};
|
||||
|
||||
/* duplicate connection, controlled by soc gpio */
|
||||
usb-vbus0-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <1 GPIO_ACTIVE_HIGH>;
|
||||
input;
|
||||
line-name = "vbus0-enable";
|
||||
};
|
||||
|
||||
usb-a-vbus1-ilimit-hog {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_LOW>;
|
||||
input;
|
||||
line-name = "vbus1-ilimit";
|
||||
};
|
||||
|
||||
/* duplicate connection, controlled by soc gpio */
|
||||
usb-vbus1-enable-hog {
|
||||
gpio-hog;
|
||||
gpios = <3 GPIO_ACTIVE_HIGH>;
|
||||
input;
|
||||
line-name = "vbus1-enable";
|
||||
};
|
||||
};
|
||||
|
||||
carrier_eeprom: eeprom@52 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x52>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
|
||||
/* usb-hub@60 */
|
||||
|
||||
/* assembly option */
|
||||
carrier_rtc: rtc@68 {
|
||||
compatible = "st,m41t83";
|
||||
reg = <0x68>;
|
||||
pinctrl-0 = <&cp1_rtc_pins>;
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&cp1_gpio1>;
|
||||
interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
|
||||
reset-gpios = <&cp1_gpio1 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
/*
|
||||
* Routed to SFP.
|
||||
* Limit to 100kHz for compatibility with SFP modules,
|
||||
* featuring AT24C01A/02/04 at addresses 0x50/0x51.
|
||||
*/
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
/*
|
||||
* SoM + Carrier each have a PHY at address 0.
|
||||
* Remove the SoM phy node, and skip adding the carrier node.
|
||||
* SGMII Auto-Negotation is enabled by bootloader for
|
||||
* autonomous operation without mdio control.
|
||||
*/
|
||||
/delete-node/ ethernet-phy@0;
|
||||
|
||||
/* U17016 */
|
||||
cp0_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
/*
|
||||
* Configure LEDs default behaviour:
|
||||
* - LED[0]: link is 1000Mbps: On (yellow)
|
||||
* - LED[1]: link/activity: On/blink (green)
|
||||
* - LED[2]: high impedance (floating)
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a17>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0 - miniPCIe */
|
||||
&cp0_pcie0 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp0_comphy0 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - M.2 B-Key (J34) */
|
||||
&cp0_pcie2 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp0_comphy5 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
pinctrl-0 = <&cp0_m2_0_shutdown_pins &cp0_mpcie_rfkill_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cp0_i2c1_pins: cp0-i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
cp0_led_pins: cp0-led-pins {
|
||||
marvell,pins = "mpp4", "mpp7";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_m2_0_shutdown_pins: cp0-m2-0-shutdown-pins {
|
||||
marvell,pins = "mpp8";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_mmc0_pins: cp0-mmc0-pins {
|
||||
marvell,pins = "mpp43", "mpp56", "mpp57", "mpp58",
|
||||
"mpp59", "mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
|
||||
cp0_mpcie_rfkill_pins: cp0-mpcie-rfkill-pins {
|
||||
marvell,pins = "mpp6";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_reg_usb_a_vbus0_pins: cp0-reg-usb-a-vbus0-pins {
|
||||
marvell,pins = "mpp27";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_reg_usb_a_vbus1_pins: cp0-reg-usb-a-vbus1-pins {
|
||||
marvell,pins = "mpp28";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_sfp0_pins: cp0-sfp0-pins {
|
||||
marvell,pins = "mpp31", "mpp32", "mpp33", "mpp34";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
};
|
||||
|
||||
/* microSD */
|
||||
&cp0_sdhci0 {
|
||||
pinctrl-0 = <&cp0_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
/* add pin for chip-select 1 */
|
||||
pinctrl-0 = <&cp0_spi1_pins &cp0_spi1_cs1_pins>;
|
||||
|
||||
flash@1 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
/* read command supports max. 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0 Host to USB-Hub */
|
||||
&cp0_usb3_0 {
|
||||
phys = <&cp0_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #4 - USB-3.0 Host to USB-Hub */
|
||||
&cp0_usb3_1 {
|
||||
phys = <&cp0_comphy4 1>, <&cp0_utmi1>;
|
||||
phy-names = "comphy", "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi1 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #4 - SFP+ 10GE */
|
||||
&cp1_eth0 {
|
||||
managed = "in-band-status";
|
||||
phy-mode = "10gbase-r";
|
||||
phys = <&cp1_comphy4 0>;
|
||||
sfp = <&sfp1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #3 - SGMII 1GE */
|
||||
&cp1_eth1 {
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
phy = <&cp1_phy0>;
|
||||
phys = <&cp0_comphy3 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - SGMII 1GE */
|
||||
&cp1_eth2 {
|
||||
managed = "in-band-status";
|
||||
phy-mode = "sgmii";
|
||||
phy = <&cp1_phy1>;
|
||||
phys = <&cp0_comphy5 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio1 {
|
||||
status = "okay";
|
||||
|
||||
/* J30 */
|
||||
m2-full-card-power-off-hog-0 {
|
||||
gpio-hog;
|
||||
gpios = <29 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "m2-full-card-power-off";
|
||||
};
|
||||
|
||||
/* J44 */
|
||||
m2-full-card-power-off-hog-1 {
|
||||
gpio-hog;
|
||||
gpios = <30 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
line-name = "m2-full-card-power-off";
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_i2c1 {
|
||||
/*
|
||||
* Routed to SFP.
|
||||
* Limit to 100kHz for compatibility with SFP modules,
|
||||
* featuring AT24C01A/02/04 at addresses 0x50/0x51.
|
||||
*/
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&cp1_i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_mdio {
|
||||
pinctrl-0 = <&cp1_mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
cp1_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
/*
|
||||
* Configure LEDs default behaviour:
|
||||
* - LED[0]: link is 1000Mbps: On (yellow)
|
||||
* - LED[1]: link/activity: On/blink (green)
|
||||
* - LED[2]: high impedance (floating)
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a17>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cp1_phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
/*
|
||||
* Configure LEDs default behaviour:
|
||||
* - LED[0]: link is 1000Mbps: On (yellow)
|
||||
* - LED[1]: link/activity: On/blink (green)
|
||||
* - LED[2]: high impedance (floating)
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0a17>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0 - M.2 (J30) */
|
||||
&cp1_pcie0 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp1_comphy0 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* SRDS #1 - SATA on M.2 (J44) */
|
||||
&cp1_sata0 {
|
||||
phys = <&cp1_comphy1 0>;
|
||||
status = "okay";
|
||||
|
||||
/* only port 0 is available */
|
||||
/delete-node/ sata-port@1;
|
||||
};
|
||||
|
||||
&cp1_syscon0 {
|
||||
cp1_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
pinctrl-0 = <&cp1_m2_1_shutdown_pins &cp1_m2_2_shutdown_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
cp1_i2c1_pins: cp0-i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
cp1_led_pins: cp1-led-pins {
|
||||
marvell,pins = "mpp54", "mpp55";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_m2_1_shutdown_pins: cp1-m2-1-shutdown-pins {
|
||||
marvell,pins = "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_m2_2_shutdown_pins: cp1-m2-2-shutdown-pins {
|
||||
marvell,pins = "mpp30";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_mdio_pins: cp1-mdio-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
cp1_rtc_pins: cp1-rtc-pins {
|
||||
marvell,pins = "mpp12", "mpp13";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_sfp1_pins: cp1-sfp1-pins {
|
||||
marvell,pins = "mpp33", "mpp34", "mpp49", "mpp50";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* SRDS #2 - USB-3.0 Host to M.2 (J44)
|
||||
* USB-2.0 Host to M.2 (J30)
|
||||
*/
|
||||
&cp1_usb3_0 {
|
||||
phys = <&cp1_comphy2 0>, <&cp1_utmi0>;
|
||||
phy-names = "comphy", "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB-2.0 Host to M.2 (J44) */
|
||||
&cp1_usb3_1 {
|
||||
phys = <&cp1_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
673
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
Normal file
673
arch/arm64/boot/dts/marvell/cn9132-clearfog.dts
Normal file
|
|
@ -0,0 +1,673 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
* DTS for SolidRun CN9132 Clearfog.
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
#include "cn9130.dtsi"
|
||||
#include "cn9132-sr-cex7.dtsi"
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9132 Clearfog";
|
||||
compatible = "solidrun,cn9132-clearfog",
|
||||
"solidrun,cn9132-sr-cex7", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet1 = &cp0_eth2;
|
||||
ethernet2 = &cp0_eth0;
|
||||
ethernet3 = &cp2_eth0;
|
||||
ethernet4 = &cp1_eth0;
|
||||
i2c7 = &carrier_mpcie_i2c;
|
||||
i2c8 = &carrier_ptp_i2c;
|
||||
mmc1 = &cp0_sdhci0;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_wake0_pins>;
|
||||
|
||||
button-0 {
|
||||
label = "SW2";
|
||||
gpios = <&cp1_gpio2 8 GPIO_ACTIVE_LOW>;
|
||||
linux,can-disable;
|
||||
linux,code = <BTN_2>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_batlow_pins &cp2_rsvd4_pins>;
|
||||
|
||||
/* LED11 */
|
||||
led-io-0 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_DISK;
|
||||
function-enumerator = <0>;
|
||||
default-state = "off";
|
||||
gpios = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* LED12 */
|
||||
led-io-1 {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_DISK;
|
||||
function-enumerator = <1>;
|
||||
default-state = "off";
|
||||
gpios = <&cp2_gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/* CON4 W_DISABLE1/W_DISABLE2 */
|
||||
rfkill-m2-wlan {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "m.2 wlan (CON4)";
|
||||
radio-type = "wlan";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_10g_phy_rst_01_pins>;
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&cp1_gpio2 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* CON5 W_DISABLE1/W_DISABLE2 */
|
||||
rfkill-m2-wlan {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "m.2 wlan (CON5)";
|
||||
radio-type = "wlan";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_10g_phy_rst_23_pins>;
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&cp1_gpio2 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* J21 W_DISABLE1 */
|
||||
rfkill-m2-wwan {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "m.2 wwan (J21)";
|
||||
radio-type = "wwan";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_rsvd3_pins>;
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* J21 W_DISABLE1 */
|
||||
rfkill-m2-gnss {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "m.2 gnss (J21)";
|
||||
radio-type = "gps";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_rsvd8_pins>;
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&cp2_gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
/* J14 W_DISABLE */
|
||||
rfkill-mpcie-wlan {
|
||||
compatible = "rfkill-gpio";
|
||||
label = "mpcie wlan (J14)";
|
||||
radio-type = "wlan";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_rsvd2_pins>;
|
||||
/* rfkill-gpio inverts internally */
|
||||
shutdown-gpios = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sfp: sfp {
|
||||
compatible = "sff,sfp";
|
||||
i2c-bus = <&com_10g_sfp_i2c0>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&com_10g_int0_pins>;
|
||||
mod-def0-gpios = <&cp0_gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
maximum-power-milliwatt = <2000>;
|
||||
};
|
||||
};
|
||||
|
||||
&com_smbus {
|
||||
/* This bus is also routed to STM32 BMC Microcontroller (U2) */
|
||||
|
||||
power-sensor@40 {
|
||||
compatible = "ti,ina220";
|
||||
reg = <0x40>;
|
||||
#io-channel-cells = <1>;
|
||||
label = "vdd_12v0";
|
||||
shunt-resistor = <2000>;
|
||||
};
|
||||
|
||||
adc@48 {
|
||||
compatible = "ti,tla2021";
|
||||
reg = <0x48>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* supplied by chaoskey hardware noise generator circuit */
|
||||
channel@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_eth_phy0 {
|
||||
/*
|
||||
* Configure LEDs default behaviour:
|
||||
* - LED[0]: link is 1000Mbps: On (yellow): 0111
|
||||
* - LED[1]: link/activity: On/Blink (green): 0001
|
||||
* - LED[2]: Off (green): 1000
|
||||
*/
|
||||
marvell,reg-init = <3 16 0xf000 0x0817>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
/* link */
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
/* act */
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
/* 1000 */
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #4 - 10GE */
|
||||
&cp0_eth0 {
|
||||
phys = <&cp0_comphy4 0>;
|
||||
phy-mode = "10gbase-r";
|
||||
managed = "in-band-status";
|
||||
sfp = <&sfp>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth2 {
|
||||
phy-mode = "2500base-x";
|
||||
phys = <&cp0_comphy5 2>;
|
||||
status = "okay";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
/*
|
||||
* Both COM and Carrier Board have a PCA9547 i2c mux at 0x77.
|
||||
* Describe them as a single device merging each child bus.
|
||||
*/
|
||||
|
||||
i2c-mux@77 {
|
||||
i2c@0 {
|
||||
/* Routed to Full PCIe (J4) */
|
||||
};
|
||||
|
||||
i2c@1 {
|
||||
/* Routed to USB Hub (U29) */
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
/* Routed to M.2 (CON4) */
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
/* Routed to M.2 (CON5) */
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
/* Routed to M.2 (J21) */
|
||||
};
|
||||
|
||||
carrier_mpcie_i2c: i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
|
||||
/* Routed to mini-PCIe (J14) */
|
||||
};
|
||||
|
||||
carrier_ptp_i2c: i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
|
||||
/* Routed to various optional PTP related components */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
ethernet-switch@4 {
|
||||
compatible = "marvell,mv88e6085";
|
||||
reg = <4>;
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sw_phy1: ethernet-phy@1 {
|
||||
reg = <0x11>;
|
||||
};
|
||||
|
||||
sw_phy2: ethernet-phy@2 {
|
||||
reg = <0x12>;
|
||||
};
|
||||
|
||||
sw_phy3: ethernet-phy@3 {
|
||||
reg = <0x13>;
|
||||
};
|
||||
|
||||
sw_phy4: ethernet-phy@4 {
|
||||
reg = <0x14>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethernet-port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
phy-handle = <&sw_phy1>;
|
||||
phy-mode = "internal";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
phy-handle = <&sw_phy2>;
|
||||
phy-mode = "internal";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
phy-handle = <&sw_phy3>;
|
||||
phy-mode = "internal";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
phy-handle = <&sw_phy4>;
|
||||
phy-mode = "internal";
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
ethernet-port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
ethernet = <&cp0_eth2>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0,#1,#2,#3 - PCIe */
|
||||
&cp0_pcie0 {
|
||||
num-lanes = <4>;
|
||||
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>, <&cp0_comphy2 0>, <&cp0_comphy3 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_pinctrl {
|
||||
/*
|
||||
* configure unused gpios exposed via pin headers:
|
||||
* - J7-10: PWRBTN
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_pwrbtn_pins>;
|
||||
};
|
||||
|
||||
/* microSD */
|
||||
&cp0_sdhci0 {
|
||||
pinctrl-0 = <&cp0_mmc0_pins>, <&cp0_mmc0_cd_pins>;
|
||||
pinctrl-names = "default";
|
||||
bus-width = <4>;
|
||||
no-1-8-v;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
/* add CS1 */
|
||||
pinctrl-0 = <&cp0_spi1_pins>, <&cp0_spi1_cs1_pins>;
|
||||
|
||||
flash@1 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
/* read command supports max. 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* J38 */
|
||||
&cp0_uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_uart2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
/* M.2 "CON5" swaps D+/D- */
|
||||
swap-dx-lanes = <1>;
|
||||
};
|
||||
|
||||
&cp1_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #2 - 5GE */
|
||||
&cp1_eth0 {
|
||||
phys = <&cp1_comphy2 0>;
|
||||
phy-mode = "5gbase-r";
|
||||
phy = <&cp1_eth_phy0>;
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #0,#1 - PCIe */
|
||||
&cp1_pcie0 {
|
||||
num-lanes = <2>;
|
||||
phys = <&cp1_comphy0 0>, <&cp1_comphy1 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #4 - PCIe */
|
||||
&cp1_pcie1 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp1_comphy4 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - PCIe */
|
||||
&cp1_pcie2 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp1_comphy5 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_pinctrl {
|
||||
/*
|
||||
* configure unused gpios exposed via pin headers:
|
||||
* - J7-8: RSVD16
|
||||
* - J7-10: THRM
|
||||
* - J10-1: WAKE1
|
||||
* - J10-2: SATA_ACT
|
||||
* - J10-8: THERMTRIP
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_rsvd16_pins &cp1_sata_act_pins &cp1_thrm_irq_pins>,
|
||||
<&cp1_thrm_trip_pins &cp1_wake1_pins>;
|
||||
};
|
||||
|
||||
/* SRDS #3 - SATA */
|
||||
&cp1_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* only port 1 is available */
|
||||
/delete-node/ sata-port@0;
|
||||
|
||||
sata-port@1 {
|
||||
phys = <&cp1_comphy3 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_utmi {
|
||||
/* M.2 "CON4" swaps D+/D- */
|
||||
swap-dx-lanes = <0>;
|
||||
};
|
||||
|
||||
&cp1_xmdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_xmdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
cp1_eth_phy0: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&com_10g_int1_pins>;
|
||||
interrupt-parent = <&cp1_gpio2>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #2 - 5GE */
|
||||
&cp2_eth0 {
|
||||
phys = <&cp2_comphy2 0>;
|
||||
phy-mode = "5gbase-r";
|
||||
phy = <&cp2_eth_phy0>;
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio1 {
|
||||
pinctrl-names= "default";
|
||||
pinctrl-0 = <&cp2_rsvd9_pins>;
|
||||
|
||||
/* J21 */
|
||||
m2-wwan-reset-hog {
|
||||
gpio-hog;
|
||||
gpios = <9 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
output-low;
|
||||
line-name = "m2-wwan-reset";
|
||||
};
|
||||
};
|
||||
|
||||
/* SRDS #0 - PCIe */
|
||||
&cp2_pcie0 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp2_comphy0 0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #4 - PCIe */
|
||||
&cp2_pcie1 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp2_comphy4 1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* SRDS #5 - PCIe */
|
||||
&cp2_pcie2 {
|
||||
num-lanes = <1>;
|
||||
phys = <&cp2_comphy5 2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_pinctrl {
|
||||
/*
|
||||
* configure unused gpios exposed via pin headers:
|
||||
* - J7-1: RSVD10
|
||||
* - J7-3: RSVD11
|
||||
* - J7-5: RSVD56
|
||||
* - J7-6: RSVD7
|
||||
* - J7-7: RSVD27
|
||||
* - J10-3: RSVD31
|
||||
* - J10-5: RSVD5
|
||||
* - J10-6: RSVD32
|
||||
* - J10-7: RSVD0
|
||||
* - J10-9: RSVD1
|
||||
*/
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_rsvd0_pins &cp2_rsvd1_pins &cp2_rsvd5_pins>,
|
||||
<&cp2_rsvd7_pins &cp2_rsvd10_pins &cp2_rsvd11_pins>,
|
||||
<&cp2_rsvd27_pins &cp2_rsvd31_pins &cp2_rsvd32_pins>,
|
||||
<&cp2_rsvd56_pins>;
|
||||
};
|
||||
|
||||
/* SRDS #3 - SATA */
|
||||
&cp2_sata0 {
|
||||
status = "okay";
|
||||
|
||||
/* only port 1 is available */
|
||||
/delete-node/ sata-port@0;
|
||||
|
||||
sata-port@1 {
|
||||
phys = <&cp2_comphy3 1>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_xmdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp2_xmdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
cp2_eth_phy0: ethernet-phy@8 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <8>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&com_10g_int2_pins>;
|
||||
interrupt-parent = <&cp2_gpio2>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
leds {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_YELLOW>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_LAN;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
712
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
Normal file
712
arch/arm64/boot/dts/marvell/cn9132-sr-cex7.dtsi
Normal file
|
|
@ -0,0 +1,712 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/*
|
||||
* Instantiate the first external CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp1
|
||||
#define CP11X_BASE f4000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f4600000
|
||||
#define CP11X_PCIE1_BASE f4620000
|
||||
#define CP11X_PCIE2_BASE f4640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
/*
|
||||
* Instantiate the second external CP115
|
||||
*/
|
||||
|
||||
#define CP11X_NAME cp2
|
||||
#define CP11X_BASE f6000000
|
||||
#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
|
||||
#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
|
||||
#define CP11X_PCIE0_BASE f6600000
|
||||
#define CP11X_PCIE1_BASE f6620000
|
||||
#define CP11X_PCIE2_BASE f6640000
|
||||
|
||||
#include "armada-cp115.dtsi"
|
||||
|
||||
#undef CP11X_NAME
|
||||
#undef CP11X_BASE
|
||||
#undef CP11X_PCIEx_MEM_BASE
|
||||
#undef CP11X_PCIEx_MEM_SIZE
|
||||
#undef CP11X_PCIE0_BASE
|
||||
#undef CP11X_PCIE1_BASE
|
||||
#undef CP11X_PCIE2_BASE
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9132 COM Express Type 7 Module";
|
||||
compatible = "solidrun,cn9132-sr-cex7", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth1;
|
||||
gpio3 = &cp1_gpio1;
|
||||
gpio4 = &cp1_gpio2;
|
||||
gpio5 = &cp2_gpio1;
|
||||
gpio6 = &cp2_gpio2;
|
||||
i2c0 = &cp0_i2c0;
|
||||
i2c1 = &cp0_i2c1;
|
||||
i2c2 = &com_clkgen_i2c;
|
||||
i2c3 = &com_10g_led_i2c;
|
||||
i2c4 = &com_10g_sfp_i2c0;
|
||||
i2c5 = &com_smbus;
|
||||
i2c6 = &com_fanctrl_i2c;
|
||||
mmc0 = &ap_sdhci0;
|
||||
rtc0 = &cp0_rtc;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
fan: pwm-fan {
|
||||
compatible = "pwm-fan";
|
||||
cooling-levels = <0 51 102 153 204 255>;
|
||||
#cooling-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_fan_pwm_pins &cp0_fan_tacho_pins>;
|
||||
pwms = <&cp0_gpio2 7 40000>;
|
||||
interrupt-parent = <&cp0_gpio1>;
|
||||
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
|
||||
};
|
||||
|
||||
v_1_8: regulator-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ap_vhv: regulator-ap-vhv-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "ap-vhv-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
pinctrl-0 = <&cp0_reg_ap_vhv_pins>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&cp0_gpio2 21 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
cp_vhv: regulator-cp-vhv-1-8 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "cp-vhv-1v8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
pinctrl-0 = <&cp0_reg_cp_vhv_pins>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&cp0_gpio2 17 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
&ap_pinctrl {
|
||||
ap_mmc0_pins: ap-mmc0-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
|
||||
marvell,function = "sdio";
|
||||
/*
|
||||
* mpp12 is emmc reset, function should be sdio (hw_rst),
|
||||
* but pinctrl-mvebu does not support this.
|
||||
*
|
||||
* From pinctrl-mvebu.h:
|
||||
* "The name will be used to switch to this setting in DT description, e.g.
|
||||
* marvell,function = "uart2". subname is only for debugging purposes."
|
||||
*/
|
||||
};
|
||||
};
|
||||
|
||||
&ap_sdhci0 {
|
||||
bus-width = <8>;
|
||||
pinctrl-0 = <&ap_mmc0_pins>;
|
||||
pinctrl-names = "default";
|
||||
vqmmc-supply = <&v_1_8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ap_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
ap_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&ap_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&ap_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_eth1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_eth1_pins>;
|
||||
phy-mode = "rgmii-id";
|
||||
phy = <&cp0_eth_phy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_gpio1 {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Tacho signal used as interrupt source by pwm-fan driver.
|
||||
* Hog IO as input to ensure mvebu-gpio irq driver`s
|
||||
* irq_set_type can succeed.
|
||||
*/
|
||||
pwm-tacho-irq-hog {
|
||||
gpio-hog;
|
||||
gpios = <26 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>;
|
||||
input;
|
||||
line-name = "fan-tacho";
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
com_eeprom: eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "atmel,spd";
|
||||
reg = <0x53>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_i2c1_pins>;
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
i2c-mux@77 {
|
||||
compatible = "nxp,pca9547";
|
||||
reg = <0x77>;
|
||||
i2c-mux-idle-disconnect;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
com_clkgen_i2c: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
|
||||
/* clock-controller@6b */
|
||||
};
|
||||
|
||||
com_10g_led_i2c: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
|
||||
/* Routed to B2B Connector as I2C_10G_LED_SCL/SDA */
|
||||
};
|
||||
|
||||
com_10g_sfp_i2c0: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
|
||||
/* Routed to B2B Connector as I2C_SFP0_CP0_SCL/SDA */
|
||||
};
|
||||
|
||||
com_smbus: i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
/* Routed to B2B Connector as SBM_CLK/DAT */
|
||||
};
|
||||
|
||||
com_fanctrl_i2c: i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
|
||||
/* fan-controller@2f (assembly option) */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_mdio {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_mdio_pins>;
|
||||
status = "okay";
|
||||
|
||||
cp0_eth_phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp0_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
/* read command supports max. 50MHz */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_syscon0 {
|
||||
cp0_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
com_10g_int0_pins: cp0-10g-int-pins {
|
||||
marvell,pins = "mpp24";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_eth1_pins: cp0-eth1-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11";
|
||||
/* docs call it "ge1", but cp110-pinctrl "ge0" */
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
cp0_fan_pwm_pins: cp0-fan-pwm-pins {
|
||||
marvell,pins = "mpp39";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_fan_tacho_pins: cp0-fan-tacho-pins {
|
||||
marvell,pins = "mpp26";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_i2c0_pins: cp0-i2c0-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
cp0_i2c1_pins: cp0-i2c1-pins {
|
||||
marvell,pins = "mpp35", "mpp36";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
cp0_mdio_pins: cp0-mdio-pins {
|
||||
marvell,pins = "mpp40", "mpp41";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
cp0_mmc0_pins: cp0-mmc0-pins {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59",
|
||||
"mpp60", "mpp61";
|
||||
marvell,function = "sdio";
|
||||
};
|
||||
|
||||
cp0_mmc0_cd_pins: cp0-mmc0-cd-pins {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "sdio_cd";
|
||||
};
|
||||
|
||||
cp0_pwrbtn_pins: cp0-pwrbtn-pins {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_reg_ap_vhv_pins: cp0-reg-ap-vhv-pins {
|
||||
marvell,pins = "mpp53";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_reg_cp_vhv_pins: cp0-reg-cp-vhv-pins {
|
||||
marvell,pins = "mpp49";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp0_spi1_pins: cp0-spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp0_spi1_cs1_pins: cp0-spi1-cs1-pins {
|
||||
marvell,pins = "mpp12";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp0_uart2_pins: cp0-uart2-pins {
|
||||
marvell,pins = "mpp50", "mpp51";
|
||||
marvell,function = "uart2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp0_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
cp0_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cp0_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cp0_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0 Host */
|
||||
&cp0_usb3_0 {
|
||||
phys = <&cp0_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB-2.0 Host */
|
||||
&cp0_usb3_1 {
|
||||
phys = <&cp0_utmi1>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp0_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp1_spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
tpm@0 {
|
||||
reg = <0>;
|
||||
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
|
||||
spi-max-frequency = <10000000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&cp1_tpm_irq_pins>;
|
||||
interrupt-parent = <&cp1_gpio1>;
|
||||
interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_syscon0 {
|
||||
cp1_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
com_10g_int1_pins: cp1-10g-int-pins {
|
||||
marvell,pins = "mpp50";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_10g_phy_rst_01_pins: cp1-10g-phy-rst-01-pins {
|
||||
marvell,pins = "mpp43";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_10g_phy_rst_23_pins: cp1-10g-phy-rst-23-pins {
|
||||
marvell,pins = "mpp42";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_batlow_pins: cp1-batlow-pins {
|
||||
marvell,pins = "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_rsvd16_pins: cp1-rsvd16-pins {
|
||||
marvell,pins = "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_sata_act_pins: cp1-sata-act-pins {
|
||||
marvell,pins = "mpp39";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_spi1_pins: cp1-spi1-pins {
|
||||
marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
cp1_thrm_irq_pins: cp1-thrm-irq-pins {
|
||||
marvell,pins = "mpp34";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_thrm_trip_pins: cp1-thrm-trip-pins {
|
||||
marvell,pins = "mpp33";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_tpm_irq_pins: cp1-tpm-irq-pins {
|
||||
marvell,pins = "mpp17";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_wake0_pins: cp1-wake0-pins {
|
||||
marvell,pins = "mpp40";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_wake1_pins: cp1-wake1-pins {
|
||||
marvell,pins = "mpp51";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp1_xmdio_pins: cp1-xmdio-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "xg";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp1_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
cp1_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cp1_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cp1_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0 Host */
|
||||
&cp1_usb3_0 {
|
||||
phys = <&cp1_utmi0>;
|
||||
phy-names = "utmi";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp1_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_ethernet {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_rtc {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&cp2_syscon0 {
|
||||
cp2_pinctrl: pinctrl {
|
||||
compatible = "marvell,cp115-standalone-pinctrl";
|
||||
|
||||
com_10g_int2_pins: cp2-10g-int-pins {
|
||||
marvell,pins = "mpp50";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd0_pins: cp2-rsvd0-pins {
|
||||
marvell,pins = "mpp0";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd1_pins: cp2-rsvd1-pins {
|
||||
marvell,pins = "mpp1";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd2_pins: cp2-rsvd2-pins {
|
||||
marvell,pins = "mpp2";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd3_pins: cp2-rsvd3-pins {
|
||||
marvell,pins = "mpp3";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd4_pins: cp2-rsvd4-pins {
|
||||
marvell,pins = "mpp4";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd5_pins: cp2-rsvd5-pins {
|
||||
marvell,pins = "mpp54";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd7_pins: cp2-rsvd7-pins {
|
||||
marvell,pins = "mpp7";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd8_pins: cp2-rsvd8-pins {
|
||||
marvell,pins = "mpp8";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd9_pins: cp2-rsvd9-pins {
|
||||
marvell,pins = "mpp9";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd10_pins: cp2-rsvd10-pins {
|
||||
marvell,pins = "mpp10";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd11_pins: cp2-rsvd11-pins {
|
||||
marvell,pins = "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd27_pins: cp2-rsvd27-pins {
|
||||
marvell,pins = "mpp11";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd31_pins: cp2-rsvd31-pins {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd32_pins: cp2-rsvd32-pins {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd55_pins: cp2-rsvd55-pins {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_rsvd56_pins: cp2-rsvd56-pins {
|
||||
marvell,pins = "mpp56";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
cp2_xmdio_pins: cp2-xmdio-pins {
|
||||
marvell,pins = "mpp37", "mpp38";
|
||||
marvell,function = "xg";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cp2_thermal_ic {
|
||||
polling-delay = <1000>;
|
||||
|
||||
trips {
|
||||
cp2_active: trip-active {
|
||||
temperature = <40000>;
|
||||
hysteresis = <4000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
|
||||
cooling-maps {
|
||||
map0 {
|
||||
trip = <&cp2_active>;
|
||||
cooling-device = <&fan THERMAL_NO_LIMIT 4>;
|
||||
};
|
||||
|
||||
map1 {
|
||||
trip = <&cp2_crit>;
|
||||
cooling-device = <&fan 4 5>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* USB-2.0/3.0 Host */
|
||||
&cp2_usb3_0 {
|
||||
phys = <&cp2_utmi0>, <&cp2_comphy1 0>;
|
||||
phy-names = "utmi", "comphy";
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cp2_utmi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* AP default console */
|
||||
&uart0 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user